From: lkcl Date: Thu, 7 Sep 2023 11:15:58 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ebc547532c33ced188c380888f8a6da2bfbbebd5;p=libreriscv.git --- diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn index 7d047ca64..2af499a1d 100644 --- a/openpower/sv/po9_encoding.mdwn +++ b/openpower/sv/po9_encoding.mdwn @@ -60,7 +60,9 @@ and is yet to be defined. Any operation that inherently makes no sense if repeated (through SVP64 Prefixing) is termed "Unvectorizable". Examples include `sc` or `sync` which have no registers. `mtmsr` is also classed -as Unvectorizable because there is only one `MSR`. +as Unvectorizable because there is only one `MSR`. Also +instructions that simply may not be Prefixed (EXT300-EXT363) are also +deemed "Unvectorizable". Unvectorizable instructions are required to be detected as such if Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction Trap raised. @@ -68,7 +70,7 @@ Unvectorizable instructions are required to be detected as such if Prefixed *Hardware Architectural Note: Given that a "pre-classification" Decode Phase is required (identifying whether the Suffix - Defined Word-instruction - is Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional), adding -"Unvectorizable" to this phase is not unreasonable.* +"Unvectorizable" detection to this phase is not unreasonable.* # New Prefixed Instruction Encoding space @@ -93,19 +95,19 @@ Key: * **x** - a `RESERVED` encoding. Illegal Instruction Trap must be raised * **n** - a future specification-defined value (currently `RESERVED`) * **!PO9** - any 6-bit binary value except Primary Opcode 9 (0b010001) -* **!ZERO** - a non-zero futre specification-defined value (currently `RESERVED`) +* **!ZERO** - a non-zero future specification-defined value (currently `RESERVED`) * **DWd** - a "Defined Word-instruction" - Book I Section 1.6 (Public v3.1 p11) * **SVRM** - a `RESERVED` encoding -* **SVP64Single**: a future `RESERVED` encoding +* **SVP64Single**: a future `RESERVED` Prefix encoding * **SVP64**: a future `RESERVED` Loop-Prefix encoding -* **EXT200-263**: a `RESERVED` encoding for future Scalar instructions -* **EXT300-363**: a `RESERVED` encoding for future Scalar instructions +* **EXT200-263**: a `RESERVED` encoding for future Scalar instructions (Vectorizable) +* **EXT300-363**: a `RESERVED` encoding for future Scalar instructions (Unvectorizable) *Architectural Resource Allocation Note: Similar to ARM's `MOVPRFX` instruction and the original x86 REP instruction, despite "influence" over the Suffix, the Suffix is entirely independent of the Prefix. Therefore **under no circumstances** must different Defined Word-instructions (different from -the same **Un-Prefixed** Defined Word-instruction) be allocated within any `EXT{z}` +the same **Un-Prefixed** Defined Word-instruction) be allocated within any `EXT{zNN}` prefixed or unprefixed space for a given value of `z` of 0, 2 or 3: the results would be catastrophic. Even if Unvectorizable an instruction Defined Word-instruction space **must** have the exact same Instruction and exact same