From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 Jul 2020 19:43:22 +0000 (+0100)
Subject: split out CompOpSubsetBase (meaning to do for a while)
X-Git-Tag: div_pipeline~37
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef61245dcd5828dff8de314406b51e7c03928937;p=soc.git

split out CompOpSubsetBase (meaning to do for a while)
---

diff --git a/src/soc/fu/base_input_record.py b/src/soc/fu/base_input_record.py
new file mode 100644
index 00000000..2b37664f
--- /dev/null
+++ b/src/soc/fu/base_input_record.py
@@ -0,0 +1,32 @@
+from nmigen.hdl.rec import Record, Layout
+from nmigen import Signal
+
+
+class CompOpSubsetBase(Record):
+    """CompOpSubsetBase
+
+    base class of subset Operation information
+    """
+    def __init__(self, layout, name):
+
+        Record.__init__(self, Layout(layout), name=name)
+
+        # grrr.  Record does not have kwargs
+        for fname, sig in self.fields.items():
+            sig.reset_less = True
+
+    def eq_from_execute1(self, other):
+        """ use this to copy in from Decode2Execute1Type
+        """
+        res = []
+        for fname, sig in self.fields.items():
+            eqfrom = other.do.fields[fname]
+            res.append(sig.eq(eqfrom))
+        return res
+
+    def ports(self):
+        res = []
+        for fname, sig in self.fields.items():
+            if isinstance(sig, Signal):
+                res.append(sig)
+        return res
diff --git a/src/soc/fu/spr/spr_input_record.py b/src/soc/fu/spr/spr_input_record.py
index 84599a98..72402d3e 100644
--- a/src/soc/fu/spr/spr_input_record.py
+++ b/src/soc/fu/spr/spr_input_record.py
@@ -1,9 +1,8 @@
-from nmigen.hdl.rec import Record, Layout
 
 from soc.decoder.power_enums import (MicrOp, Function)
+from soc.fu.base_input_record import CompOpSubsetBase
 
-
-class CompSPROpSubset(Record):
+class CompSPROpSubset(CompOpSubsetBase):
     """CompSPROpSubset
 
     a copy of the relevant subset information from Decode2Execute1Type
@@ -16,27 +15,4 @@ class CompSPROpSubset(Record):
                   ('insn', 32),
                   ('is_32bit', 1),
                   )
-
-        Record.__init__(self, Layout(layout), name=name)
-
-        # grrr.  Record does not have kwargs
-        self.insn_type.reset_less = True
-        self.insn.reset_less = True
-        self.fn_unit.reset_less = True
-        self.is_32bit.reset_less = True
-
-    def eq_from_execute1(self, other):
-        """ use this to copy in from Decode2Execute1Type
-        """
-        res = []
-        for fname, sig in self.fields.items():
-            eqfrom = other.do.fields[fname]
-            res.append(sig.eq(eqfrom))
-        return res
-
-    def ports(self):
-        return [self.insn_type,
-                self.insn,
-                self.fn_unit,
-                self.is_32bit,
-        ]
+        super().__init__(layout, name=name)