From: Luke Kenneth Casson Leighton Date: Sun, 9 Jan 2022 23:29:10 +0000 (+0000) Subject: add linux-5.7 unit test which showed a silly error: X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=efdb215ddcbdaad7f22fa2d4d44b83d3207acf3f;p=soc.git add linux-5.7 unit test which showed a silly error: LDST requests through PortInterface were truncated to 48 bits, where linux uses the top 2 bits of an address for VM/guest (Quadrant 0-3) --- diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py index 170c1b3a..b26e64b5 100644 --- a/src/soc/config/test/test_pi2ls.py +++ b/src/soc/config/test/test_pi2ls.py @@ -211,7 +211,7 @@ def tst_config_pi(testcls, ifacetype): dut = Module() pspec = TestMemPspec(ldst_ifacetype=ifacetype, imem_ifacetype='', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64) cmpi = ConfigMemoryPortInterface(pspec) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index bf35d23a..f3228214 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -189,7 +189,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): TODO: use one module for the byte-reverse as it's quite expensive in gates """ - def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset, + def __init__(self, pi=None, rwid=64, awid=64, opsubset=CompLDSTOpSubset, debugtest=False, name=None): super().__init__(rwid) self.awid = awid @@ -804,7 +804,7 @@ def test_scoreboard(): units = {} pspec = TestMemPspec(ldst_ifacetype='bare_wb', imem_ifacetype='bare_wb', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64, units=units) @@ -840,7 +840,7 @@ def test_scoreboard_regspec(): units = {} pspec = TestMemPspec(ldst_ifacetype='bare_wb', imem_ifacetype='bare_wb', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64, units=units) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index f1c895d0..42ef0610 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -43,7 +43,7 @@ import unittest class L0CacheBuffer2(Elaboratable): """L0CacheBuffer2""" - def __init__(self, n_units=8, regwid=64, addrwid=48): + def __init__(self, n_units=8, regwid=64, addrwid=64): self.n_units = n_units self.regwid = regwid self.addrwid = addrwid @@ -59,7 +59,7 @@ class L0CacheBuffer2(Elaboratable): # connect the ports as modules for i in range(self.n_units): - d = LDSTSplitter(64, 48, 4, self.dports[i]) + d = LDSTSplitter(64, 64, 4, self.dports[i]) setattr(m.submodules, "ldst_splitter%d" % i, d) # state-machine latches TODO @@ -228,7 +228,7 @@ class L0CacheBuffer(Elaboratable): by this class. That task is taken care of by LDSTCompUnit. """ - def __init__(self, n_units, pimem, regwid=64, addrwid=48): + def __init__(self, n_units, pimem, regwid=64, addrwid=64): self.n_units = n_units self.pimem = pimem self.regwid = regwid @@ -414,7 +414,7 @@ class TestL0Cache(unittest.TestCase): def test_l0_cache_test_bare_wb(self): pspec = TestMemPspec(ldst_ifacetype='test_bare_wb', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64) dut = TstL0CacheBuffer(pspec) @@ -428,7 +428,7 @@ class TestL0Cache(unittest.TestCase): def test_l0_cache_testpi(self): pspec = TestMemPspec(ldst_ifacetype='testpi', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64) dut = TstL0CacheBuffer(pspec) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index 5a3aa96d..a792e184 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -10,7 +10,7 @@ busy_o/1 most likely to be x_busy_o go_die_i/1 rst? - addr.data/48 x_addr_i (x_addr_i[:4] goes into LenExpand) + addr.data/64 x_addr_i (x_addr_i[:4] goes into LenExpand) addr.ok/1 probably x_i_valid & ~x_stall_i addr_ok_o/1 no equivalent. *might* work using x_stall_i @@ -37,7 +37,7 @@ from nmutil.util import rising_edge class Pi2LSUI(PortInterfaceBase): def __init__(self, name, lsui=None, - data_wid=64, mask_wid=8, addr_wid=48): + data_wid=64, mask_wid=8, addr_wid=64): print("pi2lsui reg mask addr", data_wid, mask_wid, addr_wid) super().__init__(data_wid, addr_wid) if lsui is None: @@ -115,7 +115,7 @@ class Pi2LSUI(PortInterfaceBase): class Pi2LSUI1(Elaboratable): def __init__(self, name, pi=None, lsui=None, - data_wid=64, mask_wid=8, addr_wid=48): + data_wid=64, mask_wid=8, addr_wid=64): print("pi2lsui reg mask addr", data_wid, mask_wid, addr_wid) self.addrbits = mask_wid if pi is None: diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 52605a14..22788af2 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -90,7 +90,7 @@ class PortInterface(RecordObject): busy_o is deasserted on the cycle AFTER st.ok is asserted. """ - def __init__(self, name=None, regwid=64, addrwid=48): + def __init__(self, name=None, regwid=64, addrwid=64): self._regwid = regwid self._addrwid = addrwid diff --git a/src/soc/experiment/test/pagetables.py b/src/soc/experiment/test/pagetables.py index c166a775..e481dd4a 100644 --- a/src/soc/experiment/test/pagetables.py +++ b/src/soc/experiment/test/pagetables.py @@ -74,3 +74,93 @@ microwatt_test5 = { 0x400000: 0x0123456badc0ffee, # not page-mapped } +# linux kernel 5.7 first MMU enable +""" + rd @ 000bf803 di b000000000001033 sel ff 3....... + rd @ 000bf804 di 0 sel ff ........ + rd @ 000bf805 di 0 sel ff ........ + rd @ 000bf806 di 10000 sel ff ........ + rd @ 000bf807 di c0000000005fc380 sel ff ........ + rd @ 000bf800 di 80000000 sel ff ........ + rd @ 000bf801 di c00000000059d400 sel ff ..Y..... + rd @ 000bf802 di c000000000000000 sel ff ........ +pc a588 insn 7c7a03a6 msr a000000000000003 +pc a58c insn 7c9b03a6 msr a000000000000003 +pc a590 insn 4c000024 msr a000000000000003 +pc a598 insn f82d0190 msr b000000000000033 + rd @ 01c00000 di ad005c0000000040 sel ff ........ + rd @ 01c00001 di 0 sel ff ........ + rd @ 01c00002 di 0 sel ff ........ + rd @ 01c00003 di 0 sel ff ........ + rd @ 01c00004 di 0 sel ff ........ + rd @ 01c00005 di 0 sel ff ........ + rd @ 01c00006 di 0 sel ff ........ + rd @ 01c00007 di 0 sel ff ........ + rd @ 000b8000 di 9e0ff0f00000080 sel ff ........ + rd @ 000b8001 di 0 sel ff ........ + rd @ 000b8002 di 0 sel ff ........ + rd @ 000b8003 di 0 sel ff ........ + rd @ 000b8004 di 0 sel ff ........ + rd @ 000b8005 di 0 sel ff ........ + rd @ 000b8006 di 0 sel ff ........ + rd @ 000b8007 di 0 sel ff ........ + rd @ 01fffc00 di 9d0ff0f00000080 sel ff ........ + rd @ 01fffc01 di 0 sel ff ........ + rd @ 01fffc02 di 0 sel ff ........ + rd @ 01fffc03 di 0 sel ff ........ + rd @ 01fffc04 di 0 sel ff ........ + rd @ 01fffc05 di 0 sel ff ........ + rd @ 01fffc06 di 0 sel ff ........ + rd @ 01fffc07 di 0 sel ff ........ + rd @ 01fffa00 di 8f010000000000c0 sel ff ........ + rd @ 01fffa01 di 8f012000000000c0 sel ff ........ + rd @ 01fffa02 di 8f014000000000c0 sel ff ........ + rd @ 01fffa03 di 8e016000000000c0 sel ff ........ + rd @ 01fffa04 di 8e018000000000c0 sel ff ........ + rd @ 01fffa05 di 8e01a000000000c0 sel ff ........ + rd @ 01fffa06 di 8e01c000000000c0 sel ff ........ + rd @ 01fffa07 di 8e01e000000000c0 sel ff ........ +""" + +microwatt_linux_5_7_boot = { + 0x000bf803<<3: 0xb000000000001033, + 0x000bf804<<3: 0x0, + 0x000bf805<<3: 0x0, + 0x000bf806<<3: 0x10000, + 0x000bf807<<3: 0xc0000000005fc380, + 0x000bf800<<3: 0x80000000, + 0x000bf801<<3: 0xc00000000059d400, + 0x000bf802<<3: 0xc000000000000000, + 0x01c00000<<3: 0xad005c0000000040, + 0x01c00001<<3: 0x0, + 0x01c00002<<3: 0x0, + 0x01c00003<<3: 0x0, + 0x01c00004<<3: 0x0, + 0x01c00005<<3: 0x0, + 0x01c00006<<3: 0x0, + 0x01c00007<<3: 0x0, + 0x000b8000<<3: 0x09e0ff0f00000080, + 0x000b8001<<3: 0x0, + 0x000b8002<<3: 0x0, + 0x000b8003<<3: 0x0, + 0x000b8004<<3: 0x0, + 0x000b8005<<3: 0x0, + 0x000b8006<<3: 0x0, + 0x000b8007<<3: 0x0, + 0x01fffc00<<3: 0x09d0ff0f00000080, + 0x01fffc01<<3: 0x0, + 0x01fffc02<<3: 0x0, + 0x01fffc03<<3: 0x0, + 0x01fffc04<<3: 0x0, + 0x01fffc05<<3: 0x0, + 0x01fffc06<<3: 0x0, + 0x01fffc07<<3: 0x0, + 0x01fffa00<<3: 0x8f010000000000c0, + 0x01fffa01<<3: 0x8f012000000000c0, + 0x01fffa02<<3: 0x8f014000000000c0, + 0x01fffa03<<3: 0x8e016000000000c0, + 0x01fffa04<<3: 0x8e018000000000c0, + 0x01fffa05<<3: 0x8e01a000000000c0, + 0x01fffa06<<3: 0x8e01c000000000c0, + 0x01fffa07<<3: 0x8e01e000000000c0, +} diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 4077451c..1f6e2097 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -411,7 +411,7 @@ def tst_single_fus_il(): def tst_all_fus(): pspec = TestMemPspec(ldst_ifacetype='testpi', imem_ifacetype='', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64) dut = AllFunctionUnits(pspec) diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index 8f36cfd8..e81dd174 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -211,7 +211,7 @@ class TestRunner(unittest.TestCase): comb = m.d.comb instruction = Signal(32) - pspec = TestMemPspec(addr_wid=48, + pspec = TestMemPspec(addr_wid=64, mask_wid=8, reg_wid=64, ) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 718b983f..74d96a87 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -1148,7 +1148,7 @@ class NonProductionCore(ControlBase): if __name__ == '__main__': pspec = TestMemPspec(ldst_ifacetype='testpi', imem_ifacetype='', - addr_wid=48, + addr_wid=64, allow_overlap=True, mask_wid=8, reg_wid=64) diff --git a/src/soc/simple/inorder.py b/src/soc/simple/inorder.py index 5262f6eb..8174fc5c 100644 --- a/src/soc/simple/inorder.py +++ b/src/soc/simple/inorder.py @@ -513,7 +513,7 @@ if __name__ == '__main__': } pspec = TestMemPspec(ldst_ifacetype='bare_wb', imem_ifacetype='bare_wb', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64, units=units) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 7f1ae097..82907d23 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -1657,7 +1657,7 @@ if __name__ == '__main__': } pspec = TestMemPspec(ldst_ifacetype='bare_wb', imem_ifacetype='bare_wb', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64, units=units) diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 7eb75f93..35ced51d 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -104,7 +104,7 @@ if __name__ == '__main__': pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype, imem_ifacetype=imem_ifacetype, - addr_wid=48, + addr_wid=64, mask_wid=8, # must leave at 64 reg_wid=64, diff --git a/src/soc/simple/test/test_issuer_linux_5_7.py b/src/soc/simple/test/test_issuer_linux_5_7.py new file mode 100644 index 00000000..6607ea52 --- /dev/null +++ b/src/soc/simple/test/test_issuer_linux_5_7.py @@ -0,0 +1,94 @@ +"""simple core test, runs instructions from a TestMemory + +related bugs: + + * https://bugs.libre-soc.org/show_bug.cgi?id=363 +""" + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git + +import unittest +import sys + +# here is the logic which takes test cases and "executes" them. +# in this instance (TestRunner) its job is to instantiate both +# a Libre-SOC nmigen-based HDL instance and an ISACaller python +# simulator. it's also responsible for performing the single +# step and comparison. +from soc.simple.test.test_runner import TestRunner + +#@platen:bookmarks +#src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase): + +# test with MMU +from openpower.test.mmu.mmu_cases import MMUTestCase +from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem +from openpower.test.ldst.ldst_cases import LDSTTestCase +from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase +#from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase) +from soc.experiment.test import pagetables + + +from openpower.simulator.program import Program +from openpower.endian import bigendian +from openpower.test.common import TestAccumulatorBase + +from openpower.consts import MSR + +from soc.experiment.test import pagetables + + +class MMUTestCase(TestAccumulatorBase): + + def case_first_vm_enabled(self): + lst = [ + "std 6,0(2)", + ] + + # set up regs + initial_regs = [0] * 32 + initial_regs[2] = 0xc0000000005fc190 + initial_regs[6] = 0x0101 + + # memory same as microwatt test + initial_mem = pagetables.microwatt_linux_5_7_boot + + # set virtual and non-privileged + # msr: 8000000000000011 + initial_msr = 0 << MSR.PR # must set "problem" state + initial_msr |= 1 << MSR.LE # little-endian + initial_msr |= 1 << MSR.SF # 64-bit + initial_msr |= 1 << MSR.DR # set "virtual" state for data + + # set PRTBL to 0xe000000 + initial_sprs = {720: 0xe000000, # PRTBL + 48: 0 # PIDR + } + + print("MMUTEST: initial_msr=",initial_msr) + self.add_case(Program(lst, bigendian), initial_regs, + initial_mem=initial_mem, + initial_sprs=initial_sprs, + initial_msr=initial_msr) + + +if __name__ == "__main__": + svp64 = True + if len(sys.argv) == 2: + if sys.argv[1] == 'nosvp64': + svp64 = False + sys.argv.pop() + + print ("SVP64 test mode enabled", svp64) + + unittest.main(exit=False) + suite = unittest.TestSuite() + + # MMU/DCache integration tests + suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64, + microwatt_mmu=True, + rom=pagetables.microwatt_linux_5_7_boot)) + + runner = unittest.TextTestRunner() + runner.run(suite) diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py index 1dd89c53..d7a82b81 100644 --- a/src/soc/simple/test/test_microwatt.py +++ b/src/soc/simple/test/test_microwatt.py @@ -62,7 +62,7 @@ class TestRunner(FHDLTestCase): pspec = TestMemPspec(ldst_ifacetype='test_bare_wb', imem_ifacetype='test_bare_wb', - addr_wid=48, + addr_wid=64, mask_wid=8, reg_wid=64, imem_test_depth=32768,