From: Andrew Waterman Date: Wed, 6 Apr 2016 17:22:20 +0000 (-0700) Subject: Fix expected misa register value for RV32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1d87fd119cbdca5c5f2016e0a156ac4f0d2347d;p=riscv-tests.git Fix expected misa register value for RV32 --- diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S index 2eeb14c..4bb0445 100644 --- a/isa/rv64mi/mcsr.S +++ b/isa/rv64mi/mcsr.S @@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN #ifdef __riscv64 TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) #else - TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30) + TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) #endif # Check that mhartid reports 0