From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Mar 2021 20:01:47 +0000 (+0000)
Subject: add link of RA_OR_ZERO SVP64 detection
X-Git-Tag: convert-csv-opcode-to-binary~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f22123446e687a4e43113d805408984a5901d65d;p=soc.git

add link of RA_OR_ZERO SVP64 detection
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index d3a66bb1..23e12f37 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -85,9 +85,13 @@ class NonProductionCore(Elaboratable):
         # instruction decoder - needs a Trap-capable Record (captures EINT etc.)
         self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand)
 
+        # SVP64 RA_OR_ZERO needs to know if the relevant EXTRA2/3 field is zero
+        self.sv_a_nz = Signal()
+
+        # state and raw instruction
         self.state = CoreState("core")
         self.raw_insn_i = Signal(32) # raw instruction
-        self.bigendian_i = Signal() # bigendian
+        self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 
         # issue/valid/busy signalling
         self.ivalid_i = Signal(reset_less=True) # instruction is valid
@@ -137,6 +141,8 @@ class NonProductionCore(Elaboratable):
             setattr(m.submodules, "dec_%s" % v.fn_name, v)
             comb += v.dec.raw_opcode_in.eq(self.raw_insn_i)
             comb += v.dec.bigendian.eq(self.bigendian_i)
+            # sigh due to SVP64 RA_OR_ZERO detection connect these too
+            comb += v.sv_a_nz.eq(self.sv_a_nz)
 
         # ssh, cheat: trap uses the main decoder because of the rewriting
         self.des[self.trapunit] = self.e.do
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index e0bd3595..71f7c1a4 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -315,6 +315,8 @@ class TestIssuerInternal(Elaboratable):
                     sync += core.state.eq(cur_state)
                     sync += core.raw_insn_i.eq(dec_opcode_i)
                     sync += core.bigendian_i.eq(self.core_bigendian_i)
+                    # set RA_OR_ZERO detection in satellite decoders
+                    sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
                     # loop into INSN_FETCH if it's a vector instruction
                     # and VL == 0.  this because VL==0 is a for-loop
                     # from 0 to 0 i.e. always, always a NOP.
@@ -399,6 +401,7 @@ class TestIssuerInternal(Elaboratable):
                 sync += core.e.eq(pdecode2.e)
                 sync += core.state.eq(cur_state)
                 sync += core.bigendian_i.eq(self.core_bigendian_i)
+                sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
                 m.next = "INSN_EXECUTE"  # move to "execute"
 
         # check if svstate needs updating: if so, write it to State Regfile