From: Daniel Benusovich Date: Fri, 23 Nov 2018 05:23:34 +0000 (-0800) Subject: Updating SV_ELWIDTH_TEST to use differing instruction formats X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f43ac5548ddea686a2c83057b860fd1622d8adbf;p=riscv-tests.git Updating SV_ELWIDTH_TEST to use differing instruction formats --- diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index e881108..dcde682 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -109,40 +109,62 @@ fmv.x.s x2, freg; \ bne x2, x1, fail; -#define SV_ELWIDTH_NONLOAD_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ - expect1, expect2, expect3 ) \ - SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ - expect1, expect2, expect3, code x28, x15, x12) \ - -#define SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ - expect1, expect2, expect3, code... ) \ - \ - load_instruction( x12, testdata , 0); \ - load_instruction( x13, testdata+elwidth , 0); \ - load_instruction( x14, testdata+elwidth*2, 0); \ - load_instruction( x15, testdata+elwidth*3, 0); \ - load_instruction( x16, testdata+elwidth*4, 0); \ - load_instruction( x17, testdata++elwidth*5, 0); \ - \ - li x28, 0xa5a5a5a5a5a5a5a5; \ - li x29, 0xa5a5a5a5a5a5a5a5; \ - li x30, 0xa5a5a5a5a5a5a5a5; \ - \ - SET_SV_MVL( vl ); \ - SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \ - SV_REG_CSR( 1, 12, wid2, 12, isvec2), \ - SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \ - SET_SV_VL( vl ); \ - \ - code; \ - \ - CLR_SV_CSRS(); \ - SET_SV_VL( 1); \ - SET_SV_MVL( 1); \ - \ - TEST_SV_IMM( x28, expect1 ); \ - TEST_SV_IMM( x29, expect2 ); \ - TEST_SV_IMM( x30, expect3 ); \ +#define SV_LOAD_FORMAT_NO_OFFSET(load_instruction, testdata, elwidth) \ + load_instruction( x12, testdata); \ + load_instruction( x13, testdata+elwidth); \ + load_instruction( x14, testdata+elwidth*2); \ + load_instruction( x15, testdata+elwidth*3); \ + load_instruction( x16, testdata+elwidth*4); \ + load_instruction( x17, testdata++elwidth*5); \ + +#define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth) \ + load_instruction( x12, testdata, 0); \ + load_instruction( x13, testdata+elwidth, 0); \ + load_instruction( x14, testdata+elwidth*2, 0); \ + load_instruction( x15, testdata+elwidth*3, 0); \ + load_instruction( x16, testdata+elwidth*4, 0); \ + load_instruction( x17, testdata+elwidth*5, 0); \ + +#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, \ + vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3 ) \ + \ + SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth), \ + vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3, code x28, x15, x12) \ + +#define SV_ELWIDTH_TEST_LOAD(code, load_instruction, testdata, elwidth, \ + vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3 ) \ + \ + SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_NO_OFFSET(load_instruction, testdata, elwidth), \ + vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \ + expect1, expect2, expect3, code x28, x15, x12) \ + +#define SV_ELWIDTH_TEST_INNER(load_type, vl, wid1, wid2, wid3, \ + isvec1, isvec2, isvec3, \ + expect1, expect2, expect3, code... ) \ + load_type; \ + \ + li x28, 0xa5a5a5a5a5a5a5a5; \ + li x29, 0xa5a5a5a5a5a5a5a5; \ + li x30, 0xa5a5a5a5a5a5a5a5; \ + \ + SET_SV_MVL( vl ); \ + SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \ + SV_REG_CSR( 1, 12, wid2, 12, isvec2), \ + SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \ + SET_SV_VL( vl ); \ + \ + code; \ + \ + CLR_SV_CSRS(); \ + SET_SV_VL( 1); \ + SET_SV_MVL( 1); \ + \ + TEST_SV_IMM( x28, expect1 ); \ + TEST_SV_IMM( x29, expect2 ); \ + TEST_SV_IMM( x30, expect3 ); \ #define SV_W_DFLT 0 #define SV_W_8BIT 1