From: Henry Styles Date: Tue, 8 Aug 2017 00:34:01 +0000 (-0700) Subject: U500DevKit 4GB DIMM Wip X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9437b2c7e53fd83e3227095face80b8393cb104;p=sifive-blocks.git U500DevKit 4GB DIMM Wip --- diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala index afaff33..7d864e4 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala @@ -10,15 +10,16 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} -trait HasXilinxVC707MIGParameters { -} +case class XilinxVC707MIGParams( + depthGB : Int +) -class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR +class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB) -class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR - with VC707MIGIOClocksReset +class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset -class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters { +class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule { + require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only") val device = new MemoryDevice val node = TLInputNode() val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters( @@ -48,12 +49,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC lazy val module = new LazyModuleImp(this) { val io = new Bundle { - val port = new XilinxVC707MIGIO + val port = new XilinxVC707MIGIO(c.depthGB) val tl = node.bundleIn } //MIG black box instantiation - val blackbox = Module(new vc707mig) + val blackbox = Module(new vc707mig(c.depthGB)) //pins to top level diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala index 068f64c..59dd4a0 100644 --- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala +++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala @@ -2,13 +2,16 @@ package sifive.blocks.devices.xilinxvc707mig import Chisel._ +import freechips.rocketchip.config._ import freechips.rocketchip.coreplex.HasMemoryBus import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} +case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams] + trait HasMemoryXilinxVC707MIG extends HasMemoryBus { val module: HasMemoryXilinxVC707MIGModuleImp - val xilinxvc707mig = LazyModule(new XilinxVC707MIG) + val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey))) require(nMemoryChannels == 1, "Coreplex must have 1 master memory port") xilinxvc707mig.node := memBuses.head.toDRAMController @@ -24,7 +27,7 @@ trait HasMemoryXilinxVC707MIGBundle { trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp with HasMemoryXilinxVC707MIGBundle { val outer: HasMemoryXilinxVC707MIG - val xilinxvc707mig = IO(new XilinxVC707MIGIO) + val xilinxvc707mig = IO(new XilinxVC707MIGIO(p(MemoryXilinxDDRKey).depthGB)) xilinxvc707mig <> outer.xilinxvc707mig.module.io.port } diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala index 1e01748..0957d53 100644 --- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala +++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala @@ -3,13 +3,15 @@ package sifive.blocks.ip.xilinx.vc707mig import Chisel._ import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.util.GenericParameterizedBundle import freechips.rocketchip.config._ // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0 // Black Box -trait VC707MIGIODDR extends Bundle { - val ddr3_addr = Bits(OUTPUT,14) +class VC707MIGIODDR(depthGB : Integer) extends GenericParameterizedBundle(depthGB) { + require((depthGB==1) || (depthGB==4),"VC707MIGIODDR supports 1GB and 4GB depth configuraton only") + val ddr3_addr = Bits(OUTPUT,if(depthGB==1) 14 else 16) val ddr3_ba = Bits(OUTPUT,3) val ddr3_ras_n = Bool(OUTPUT) val ddr3_cas_n = Bool(OUTPUT) @@ -44,10 +46,13 @@ trait VC707MIGIOClocksReset extends Bundle { //scalastyle:off //turn off linter: blackbox name must match verilog module -class vc707mig(implicit val p:Parameters) extends BlackBox +class vc707mig(depthGB : Integer)(implicit val p:Parameters) extends BlackBox { - val io = new Bundle with VC707MIGIODDR - with VC707MIGIOClocksReset { + require((depthGB==1) || (depthGB==4),"vc707mig supports 1GB and 4GB depth configuraton only") + + override def desiredName = if(depthGB==4) "vc707mig4gb" else "vc707mig" + + val io = new VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset { // User interface signals val app_sr_req = Bool(INPUT) val app_ref_req = Bool(INPUT) @@ -58,7 +63,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox //axi_s //slave interface write address ports val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,30) + val s_axi_awaddr = Bits(INPUT,if(depthGB==1) 30 else 32) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) val s_axi_awburst = Bits(INPUT,2) @@ -81,7 +86,7 @@ class vc707mig(implicit val p:Parameters) extends BlackBox val s_axi_bvalid = Bool(OUTPUT) //slave interface read address ports val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,30) + val s_axi_araddr = Bits(INPUT,if(depthGB==1) 30 else 32) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) val s_axi_arburst = Bits(INPUT,2)