From: lkcl Date: Wed, 3 Mar 2021 13:39:46 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~95 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f9c4772ff85be885dee6a30f59740d190eaa01e9;p=libreriscv.git --- diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index e2d2f3de7..4d4f859da 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -35,7 +35,7 @@ instructions: setvli r0, MVL=64, VL=64 ld r0.v, 0(r30) # load 64 registers from memory -Page Faults etc. aside this is *guaranteed* 100% without fail to perform 64 unit-strided LDs starting from the address pointed to by r30 and put the contents into r0 through r63. Thus it becomes a "LOAD-MULTI". Twin Predication could even be used to only load relevant registers from the stack. This *only works if VL is set to the requested value* (caveat being, limited to not exceed MVL) +Page Faults etc. aside this is *guaranteed* 100% without fail to perform 64 unit-strided LDs starting from the address pointed to by r30 and put the contents into r0 through r63. Thus it becomes a "LOAD-MULTI". Twin Predication could even be used to only load relevant registers from the stack. This *only works if VL is set to the requested value* rather than, as in RVV, allowing the hardware to set VL to an arbitrary value (caveat being, limited to not exceed MVL) # Format