From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 20 Jul 2018 06:55:31 +0000 (+0100)
Subject: add mkslow_peripherals
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fa4b8534992c80a17482c2789e2c403566328c6e;p=pinmux.git

add mkslow_peripherals
---

diff --git a/src/bsv/bsv_lib/slow_peripherals_template.bsv b/src/bsv/bsv_lib/slow_peripherals_template.bsv
index 921ea0c..3bd94be 100644
--- a/src/bsv/bsv_lib/slow_peripherals_template.bsv
+++ b/src/bsv/bsv_lib/slow_peripherals_template.bsv
@@ -87,13 +87,7 @@ package slow_peripherals;
 		Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
 
 		/*======= Module declarations for each peripheral =======*/
-		`ifdef UART0
-			Uart16550_AXI4_Lite_Ifc uart0 <- mkUart16550(clocked_by uart_clock, reset_by uart_reset, sp_clock, sp_reset);
-		`endif
-		`ifdef UART1
-			//Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by uart_clock, reset_by uart_reset,sp_clock, sp_reset);
-			Ifc_Uart_bs uart1 <- mkUart_bs(clocked_by sp_clock, reset_by sp_reset,sp_clock, sp_reset);
-		`endif
+{5}
 		`ifdef CLINT
 			Ifc_clint				clint				<- mkclint();
 		`endif
@@ -102,30 +96,11 @@ package slow_peripherals;
          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 			  Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
 		`endif
-		`ifdef I2C0 
-			I2C_IFC					i2c0				<- mkI2CController();
-		`endif
-		`ifdef I2C1
-			I2C_IFC					i2c1				<- mkI2CController();
-		`endif
-		`ifdef QSPI0 
-			Ifc_qspi			qspi0				<-	mkqspi(); 
-		`endif
-		`ifdef QSPI1 
-			Ifc_qspi			qspi1				<-	mkqspi(); 
-		`endif
 		`ifdef AXIEXP
 			Ifc_AxiExpansion		axiexp1			<- mkAxiExpansion();	
 		`endif
-    `ifdef PWM_AXI4Lite
-      Ifc_PWM_bus pwm_bus <- mkPWM_bus(ext_pwm_clock);
-    `endif
-    // NEEL EDIT
     Ifc_pinmux pinmux <- mkpinmux; // mandatory
-    MUX#(3) muxa <- mkmux(); // mandatory. number depends on the number of instances required.
-    GPIO#(3) gpioa <- mkgpio(); // optional. depends the number of IO pins declared before.
     Wire#(Bit#(32)) wr_interrupt <- mkWire();
-    // NEEL EDIT OVER
 		/*=======================================================*/
 
    	AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)	slow_fabric <- 
diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index 1a86b70..de74bac 100644
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -53,7 +53,7 @@ class uart(PBase):
         return 8
 
     def mkslow_peripheral(self):
-        return "            Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
+        return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
                "                mkUart16550(clocked_by uart_clock,\n" + \
                "                    reset_by uart_reset, sp_clock, sp_reset);"
 
@@ -194,6 +194,11 @@ class PeripheralIface(object):
             return ''
         return self.slow.axi_addr_map(self.ifacename, count)
 
+    def mkslow_periph(self, count):
+        if not self.slow:
+            return ''
+        return self.slow.mkslow_peripheral().format(count, self.ifacename)
+
 class PeripheralInterfaces(object):
     def __init__(self):
         pass
@@ -243,6 +248,13 @@ class PeripheralInterfaces(object):
                 ret.append(self.data[name].axi_addr_map(i))
         return '\n'.join(list(filter(None, ret)))
 
+    def mkslow_periph(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                ret.append(self.data[name].mkslow_periph(i))
+        return '\n'.join(list(filter(None, ret)))
+
 
 class PFactory(object):
     def getcls(self, name):
diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index abfb0bb..b919719 100644
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -104,9 +104,10 @@ def write_slow(slow, template, p, ifaces):
     regdef = ifaces.axi_reg_def()
     slavedecl = ifaces.axi_slave_idx()
     fnaddrmap = ifaces.axi_addr_map()
+    mkslow = ifaces.mkslow_periph()
     with open(slow, "w") as bsv_file:
         bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
-                                       fnaddrmap))
+                                       fnaddrmap, mkslow))
 
 
 def write_bus(bus, p, ifaces):