From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Jan 2022 17:19:47 +0000 (+0000)
Subject: fix DriverConflict over MSR write in Issuer/Core by providing an
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc6af14c284b695426770b1d14e6e7f2b0422d0d;p=soc.git

fix DriverConflict over MSR write in Issuer/Core by providing an
extra write-port to StateRegs
---

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index df2fd4a8..754b6902 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -76,12 +76,23 @@ class StateRegs(RegFileArray, StateRegsEnum):
         create_ports(self, wr_spec, rd_spec)
 
     def get_port_specs(self):
-        w_port_spec = {'nia': "nia",
+        w_port_spec = { # these 3 allow writing state by Function Units
+                        # strictly speaking this should not be allowed,
+                        # the information should be passed back to Issuer
+                        # to work out what to do
+                        'nia': "nia",
                         'msr': "msr",
                         'svstate': "svstate",
-                        'sv': "sv", # writing SVSTATE (issuer)
-                        'd_wr1': "d_wr1"} # writing PC (issuer)
-        r_port_spec = {'cia': "cia", # reading PC (issuer)
+                        # these 3 allow writing state by Issuer
+                        'sv': "sv", # writing SVSTATE
+                        'd_wr1': "d_wr1", # writing PC
+                        'd_wr2': "d_wr2"} # writing MSR
+        r_port_spec = { # these are for reading state by Issuer but
+                        # the FUs do not read them: they are passed in
+                        # because of multi-issue / pipelining / etc.
+                        # the state could be totally different and is
+                        # only known *at* issue time, *by* the issuer
+                        'cia': "cia", # reading PC (issuer)
                         'msr': "msr", # reading MSR (issuer)
                         'sv': "sv", # reading SV (issuer)
                         }
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 08951c57..aa2a6eef 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -285,7 +285,7 @@ class TestIssuerBase(Elaboratable):
         self.state_r_pc = staterf.r_ports['cia']  # PC rd
         self.state_r_sv = staterf.r_ports['sv']  # SVSTATE rd
 
-        self.state_w_msr = staterf.w_ports['msr']  # MSR wr
+        self.state_w_msr = staterf.w_ports['d_wr2']  # MSR wr
         self.state_w_pc = staterf.w_ports['d_wr1']  # PC wr
         self.state_w_sv = staterf.w_ports['sv']  # SVSTATE wr