From: Tim Newsome <tim@sifive.com>
Date: Tue, 3 May 2016 01:07:51 +0000 (-0700)
Subject: Add dret.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fdc92ba2c5ad75abf1e86c87ea23fb7d7dd00ca1;p=riscv-isa-sim.git

Add dret.
---

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 35dd406..e7e99d0 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -71,8 +71,7 @@ check_halt:
 exit:
         # Restore s0.
         csrr    s0, DSCRATCH
-        # TODO: dret?
-        sret
+        dret
 
 
 _entry:
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index 8b5ea69..42fda2b 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -6,7 +6,7 @@ static const unsigned char debug_rom_raw[] = {
   0x93, 0x94, 0x14, 0x00, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x34, 0x80, 0x43,
   0x6f, 0x00, 0xc0, 0x00, 0x13, 0x00, 0x00, 0x00, 0x23, 0x2e, 0x80, 0x42,
   0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x84, 0x00, 0x63, 0x04, 0x04, 0x00,
-  0x6f, 0x00, 0x40, 0x05, 0x73, 0x24, 0x20, 0x79, 0x73, 0x00, 0x00, 0x10,
+  0x6f, 0x00, 0x40, 0x05, 0x73, 0x24, 0x20, 0x79, 0x73, 0x00, 0x20, 0x79,
   0x73, 0x10, 0x24, 0x79, 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x74, 0x00,
   0x13, 0x04, 0xd4, 0xff, 0x63, 0x16, 0x04, 0x02, 0x73, 0x24, 0x00, 0xf1,
   0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40,
diff --git a/riscv/encoding.h b/riscv/encoding.h
index bdba5f2..ea45e54 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -363,6 +363,8 @@
 #define MASK_HRET  0xffffffff
 #define MATCH_MRET 0x30200073
 #define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x79200073
+#define MASK_DRET  0xffffffff
 #define MATCH_SFENCE_VM 0x10400073
 #define MASK_SFENCE_VM  0xfff07fff
 #define MATCH_WFI 0x10500073
@@ -672,6 +674,9 @@
 #define CSR_MSCYCLE_DELTA 0x704
 #define CSR_MSTIME_DELTA 0x705
 #define CSR_MSINSTRET_DELTA 0x706
+#define CSR_DCSR 0x790
+#define CSR_DPC 0x791
+#define CSR_DSCRATCH 0x792
 #define CSR_MCYCLE 0xf00
 #define CSR_MTIME 0xf01
 #define CSR_MINSTRET 0xf02
@@ -799,6 +804,7 @@ DECLARE_INSN(uret, MATCH_URET, MASK_URET)
 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
@@ -974,6 +980,9 @@ DECLARE_CSR(muinstret_delta, CSR_MUINSTRET_DELTA)
 DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA)
 DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA)
 DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
 DECLARE_CSR(mcycle, CSR_MCYCLE)
 DECLARE_CSR(mtime, CSR_MTIME)
 DECLARE_CSR(minstret, CSR_MINSTRET)
diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h
new file mode 100644
index 0000000..6cfd1e2
--- /dev/null
+++ b/riscv/insns/dret.h
@@ -0,0 +1,6 @@
+require_privilege(PRV_M);
+set_pc_and_serialize(STATE.dpc);
+p->set_privilege(STATE.dcsr.prv);
+
+/* We're not in Debug Mode anymore. */
+STATE.dcsr.cause = 0;
diff --git a/riscv/insns/sret.h b/riscv/insns/sret.h
index dc2fee0..f5e89e4 100644
--- a/riscv/insns/sret.h
+++ b/riscv/insns/sret.h
@@ -7,6 +7,3 @@ s = set_field(s, MSTATUS_SPIE, 0);
 s = set_field(s, MSTATUS_SPP, PRV_U);
 p->set_privilege(prev_prv);
 p->set_csr(CSR_MSTATUS, s);
-
-/* We're not in Debug Mode anymore. */
-STATE.dcsr.cause = 0;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index f09eea8..f98d0a0 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -198,7 +198,7 @@ void processor_t::enter_debug_mode(uint8_t cause)
   fprintf(stderr, "enter_debug_mode(%d)\n", cause);
   state.dcsr.cause = cause;
   state.dcsr.prv = state.prv;
-  state.prv = PRV_M;
+  set_privilege(PRV_M);
   state.dpc = state.pc;
   state.pc = DEBUG_ROM_START;
   debug = true; // TODO
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 279fbde..65f8c99 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -134,6 +134,7 @@ riscv_insn_list = \
 	divu \
 	divuw \
 	divw \
+	dret \
 	ebreak \
 	ecall \
 	fadd_d \