From: Michael Nolan Date: Mon, 30 Mar 2020 17:03:59 +0000 (-0400) Subject: Fix tests broken by df295b5 X-Git-Tag: div_pipeline~1597 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ff3ac82b1f6e9973e3a8152bc187b7ed70a5ff85;p=soc.git Fix tests broken by df295b5 --- diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py index f84fab17..981a4d22 100644 --- a/src/soc/decoder/formal/proof_decoder2.py +++ b/src/soc/decoder/formal/proof_decoder2.py @@ -72,7 +72,7 @@ class Driver(Elaboratable): with m.If(dec.op.in2_sel == In2Sel.RB): comb += Assert(pdecode2.e.read_reg2.ok == 1) comb += Assert(pdecode2.e.read_reg2.data == - dec.RB[0:-1]) + dec.RB) with m.Elif(dec.op.in2_sel == In2Sel.NONE): comb += Assert(pdecode2.e.imm_data.ok == 0) comb += Assert(pdecode2.e.read_reg2.ok == 0) @@ -80,7 +80,7 @@ class Driver(Elaboratable): comb += Assert(pdecode2.e.imm_data.ok == 0) comb += Assert(pdecode2.e.read_reg2.ok == 0) comb += Assert(pdecode2.e.read_spr2.ok == 1) - with m.If(dec.FormXL.XO[9]): + with m.If(dec.fields.FormXL.XO[9]): comb += Assert(pdecode2.e.read_spr2.data == SPR.CTR) with m.Else(): comb += Assert(pdecode2.e.read_spr2.data == SPR.LR) @@ -88,31 +88,31 @@ class Driver(Elaboratable): comb += Assert(pdecode2.e.imm_data.ok == 1) with m.Switch(dec.op.in2_sel): with m.Case(In2Sel.CONST_UI): - comb += Assert(pdecode2.e.imm_data.data == dec.UI[0:-1]) + comb += Assert(pdecode2.e.imm_data.data == dec.UI) with m.Case(In2Sel.CONST_SI): comb += Assert(pdecode2.e.imm_data.data == - self.exts(dec.SI[0:-1], 16, 64)) + self.exts(dec.SI, 16, 64)) with m.Case(In2Sel.CONST_UI_HI): comb += Assert(pdecode2.e.imm_data.data == - (dec.UI[0:-1] << 16)) + (dec.UI << 16)) with m.Case(In2Sel.CONST_SI_HI): comb += Assert(pdecode2.e.imm_data.data == - self.exts(dec.SI[0:-1] << 16, 32, 64)) + self.exts(dec.SI << 16, 32, 64)) with m.Case(In2Sel.CONST_LI): comb += Assert(pdecode2.e.imm_data.data == - (dec.LI[0:-1] << 2)) + (dec.LI << 2)) with m.Case(In2Sel.CONST_BD): comb += Assert(pdecode2.e.imm_data.data == - (dec.BD[0:-1] << 2)) + (dec.BD << 2)) with m.Case(In2Sel.CONST_DS): comb += Assert(pdecode2.e.imm_data.data == - (dec.DS[0:-1] << 2)) + (dec.DS << 2)) with m.Case(In2Sel.CONST_M1): comb += Assert(pdecode2.e.imm_data.data == ~0) with m.Case(In2Sel.CONST_SH): - comb += Assert(pdecode2.e.imm_data.data == dec.sh[0:-1]) + comb += Assert(pdecode2.e.imm_data.data == dec.sh) with m.Case(In2Sel.CONST_SH32): - comb += Assert(pdecode2.e.imm_data.data == dec.SH32[0:-1]) + comb += Assert(pdecode2.e.imm_data.data == dec.SH32) with m.Default(): comb += Assert(0) @@ -127,15 +127,15 @@ class Driver(Elaboratable): comb = self.comb dec = m.submodules.pdecode2.dec - comb += Assert(dec.RB[0:-1] == self.instr_bits(16, 20)) - comb += Assert(dec.UI[0:-1] == self.instr_bits(16, 31)) - comb += Assert(dec.SI[0:-1] == self.instr_bits(16, 31)) - comb += Assert(dec.LI[0:-1] == self.instr_bits(6, 29)) - comb += Assert(dec.BD[0:-1] == self.instr_bits(16, 29)) - comb += Assert(dec.DS[0:-1] == self.instr_bits(16, 29)) - comb += Assert(dec.sh[0:-1] == Cat(self.instr_bits(16, 20), + comb += Assert(dec.RB == self.instr_bits(16, 20)) + comb += Assert(dec.UI == self.instr_bits(16, 31)) + comb += Assert(dec.SI == self.instr_bits(16, 31)) + comb += Assert(dec.LI == self.instr_bits(6, 29)) + comb += Assert(dec.BD == self.instr_bits(16, 29)) + comb += Assert(dec.DS == self.instr_bits(16, 29)) + comb += Assert(dec.sh == Cat(self.instr_bits(16, 20), self.instr_bits(30))) - comb += Assert(dec.SH32[0:-1] == self.instr_bits(16, 20)) + comb += Assert(dec.SH32 == self.instr_bits(16, 20)) def test_in3(self): m = self.m @@ -181,10 +181,10 @@ class Driver(Elaboratable): comb += Assert(pdecode2.e.rc.data == 1) with m.If(sel == RC.RC): comb += Assert(pdecode2.e.rc.data == - dec.Rc[0:-1]) + dec.Rc) comb += Assert(pdecode2.e.oe.ok == 1) comb += Assert(pdecode2.e.oe.data == - dec.OE[0:-1]) + dec.OE) def test_single_bits(self): m = self.m diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 27b520c0..5524ce1e 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -33,7 +33,7 @@ class DecodeA(Elaboratable): # select Register A field ra = Signal(5, reset_less=True) - comb += ra.eq(self.dec.RA[0:-1]) + comb += ra.eq(self.dec.RA) with m.If((self.sel_in == In1Sel.RA) | ((self.sel_in == In1Sel.RA_OR_ZERO) & (ra != Const(0, 5)))): @@ -56,7 +56,7 @@ class DecodeA(Elaboratable): # MFSPR or MTSPR: move-from / move-to SPRs with m.If((op.internal_op == InternalOp.OP_MFSPR) | (op.internal_op == InternalOp.OP_MTSPR)): - comb += self.spr_out.data.eq(self.dec.SPR[0:-1]) # SPR field, XFX + comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX comb += self.spr_out.ok.eq(1) return m @@ -105,40 +105,40 @@ class DecodeB(Elaboratable): # select Register B field with m.Switch(self.sel_in): with m.Case(In2Sel.RB): - comb += self.reg_out.data.eq(self.dec.RB[0:-1]) + comb += self.reg_out.data.eq(self.dec.RB) comb += self.reg_out.ok.eq(1) with m.Case(In2Sel.CONST_UI): - comb += self.imm_out.data.eq(self.dec.UI[0:-1]) + comb += self.imm_out.data.eq(self.dec.UI) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here? comb += self.imm_out.data.eq( - self.exts(self.dec.SI[0:-1], 16, 64)) + self.exts(self.dec.SI, 16, 64)) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_UI_HI): - comb += self.imm_out.data.eq(self.dec.UI[0:-1]<<16) + comb += self.imm_out.data.eq(self.dec.UI<<16) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here? - comb += self.imm_out.data.eq(self.dec.SI[0:-1]<<16) + comb += self.imm_out.data.eq(self.dec.SI<<16) comb += self.imm_out.data.eq( - self.exts(self.dec.SI[0:-1] << 16, 32, 64)) + self.exts(self.dec.SI << 16, 32, 64)) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_LI): - comb += self.imm_out.data.eq(self.dec.LI[0:-1]<<2) + comb += self.imm_out.data.eq(self.dec.LI<<2) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_BD): - comb += self.imm_out.data.eq(self.dec.BD[0:-1]<<2) + comb += self.imm_out.data.eq(self.dec.BD<<2) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_DS): - comb += self.imm_out.data.eq(self.dec.DS[0:-1]<<2) + comb += self.imm_out.data.eq(self.dec.DS<<2) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_M1): comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_SH): - comb += self.imm_out.data.eq(self.dec.sh[0:-1]) + comb += self.imm_out.data.eq(self.dec.sh) comb += self.imm_out.ok.eq(1) with m.Case(In2Sel.CONST_SH32): - comb += self.imm_out.data.eq(self.dec.SH32[0:-1]) + comb += self.imm_out.data.eq(self.dec.SH32) comb += self.imm_out.ok.eq(1) # decode SPR2 based on instruction type @@ -172,7 +172,7 @@ class DecodeC(Elaboratable): # select Register C field with m.If(self.sel_in == In3Sel.RS): - comb += self.reg_out.data.eq(self.dec.RS[0:-1]) + comb += self.reg_out.data.eq(self.dec.RS) comb += self.reg_out.ok.eq(1) return m @@ -198,13 +198,13 @@ class DecodeOut(Elaboratable): # select Register out field with m.Switch(self.sel_in): with m.Case(OutSel.RT): - comb += self.reg_out.data.eq(self.dec.RT[0:-1]) + comb += self.reg_out.data.eq(self.dec.RT) comb += self.reg_out.ok.eq(1) with m.Case(OutSel.RA): - comb += self.reg_out.data.eq(self.dec.RA[0:-1]) + comb += self.reg_out.data.eq(self.dec.RA) comb += self.reg_out.ok.eq(1) with m.Case(OutSel.SPR): - comb += self.spr_out.data.eq(self.dec.SPR[0:-1]) # from XFX + comb += self.spr_out.data.eq(self.dec.SPR) # from XFX comb += self.spr_out.ok.eq(1) return m @@ -228,7 +228,7 @@ class DecodeRC(Elaboratable): # select Record bit out field with m.Switch(self.sel_in): with m.Case(RC.RC): - comb += self.rc_out.data.eq(self.dec.Rc[0:-1]) + comb += self.rc_out.data.eq(self.dec.Rc) comb += self.rc_out.ok.eq(1) with m.Case(RC.ONE): comb += self.rc_out.data.eq(1) @@ -264,7 +264,7 @@ class DecodeOE(Elaboratable): # select OE bit out field with m.Switch(self.sel_in): with m.Case(RC.RC): - comb += self.oe_out.data.eq(self.dec.OE[0:-1]) + comb += self.oe_out.data.eq(self.dec.OE) comb += self.oe_out.ok.eq(1) return m @@ -421,7 +421,7 @@ class PowerDecode2(Elaboratable): comb += self.e.is_32bit.eq(self.dec.op.is_32b) comb += self.e.is_signed.eq(self.dec.op.sgn) with m.If(self.dec.op.lk): - comb += self.e.lk.eq(self.dec.LK[0:-1]) # XXX TODO: accessor + comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor comb += self.e.byte_reverse.eq(self.dec.op.br) comb += self.e.sign_extend.eq(self.dec.op.sgn_ext) diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py index 9238d387..aca254e4 100644 --- a/src/soc/decoder/test/test_decoder_gas.py +++ b/src/soc/decoder/test/test_decoder_gas.py @@ -213,7 +213,7 @@ class CmpRegOp: def check_results(self, pdecode2): r1sel = yield pdecode2.e.read_reg1.data r2sel = yield pdecode2.e.read_reg2.data - crsel = yield pdecode2.dec.BF[0:-1] + crsel = yield pdecode2.dec.BF assert(r1sel == self.r1.num) assert(r2sel == self.r2.num) @@ -253,11 +253,11 @@ class RotateOp: dec = pdecode2.dec if "i" in self.opcodestr: - shift = yield dec.SH[0:-1] + shift = yield dec.SH else: shift = yield pdecode2.e.read_reg2.data - mb = yield dec.MB[0:-1] - me = yield dec.ME[0:-1] + mb = yield dec.MB + me = yield dec.ME assert(r1sel == self.r1.num) assert(r2sel == self.r2.num) @@ -298,7 +298,7 @@ class Branch: assert(lk == 1) else: assert(lk == 0) - aa = yield pdecode2.dec.AA[0:-1] + aa = yield pdecode2.dec.AA if "a" in self.opcodestr: assert(aa == 1) else: @@ -332,8 +332,8 @@ class BranchCond: def check_results(self, pdecode2): imm = yield pdecode2.e.imm_data.data - bo = yield pdecode2.dec.BO[0:-1] - bi = yield pdecode2.dec.BI[0:-1] + bo = yield pdecode2.dec.BO + bi = yield pdecode2.dec.BI assert(imm == self.addr) assert(bo == self.bo) @@ -343,7 +343,7 @@ class BranchCond: assert(lk == 1) else: assert(lk == 0) - aa = yield pdecode2.dec.AA[0:-1] + aa = yield pdecode2.dec.AA if "a" in self.opcodestr: assert(aa == 1) else: @@ -375,8 +375,8 @@ class BranchRel: return string def check_results(self, pdecode2): - bo = yield pdecode2.dec.BO[0:-1] - bi = yield pdecode2.dec.BI[0:-1] + bo = yield pdecode2.dec.BO + bi = yield pdecode2.dec.BI assert(bo == self.bo) assert(bi == self.bi)