From: Yunsup Lee Date: Sat, 25 Mar 2017 04:38:31 +0000 (-0700) Subject: rename l2FrontendBus as fsb X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=refs%2Fheads%2Fspi_delay_hack;p=sifive-blocks.git rename l2FrontendBus as fsb --- diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index f37f7f9..d64d19a 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) - l2FrontendBus.node := xilinxvc707pcie.master + fsb.node := xilinxvc707pcie.master xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) intBus.intnode := xilinxvc707pcie.intnode