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build/sim: allow for arbitrary clocks generation using clockers
[litex.git] / litex / build / sim / core / veril.h
2020-08-03 Jędrzej Boczarbuild/sim: allow for arbitrary clocks generation using... blob | commitdiff | raw
2020-08-03 Jędrzej Boczarbuild/sim: use a real timebase in the simulation blob | commitdiff | raw | diff to current
2020-05-27 enjoy-digitalMerge pull request #541 from antmicro/jboc/spd-read blob | commitdiff | raw | diff to current
2020-05-25 enjoy-digitalMerge pull request #539 from dayjaby/pr-fix_uart_startbit blob | commitdiff | raw | diff to current
2020-05-22 enjoy-digitalMerge pull request #535 from antmicro/arty-cv32e40p blob | commitdiff | raw | diff to current
2020-05-21 Florent Kermarrecbuild/sim: rename dut to sim (for consistency with... blob | commitdiff | raw | diff to current
2020-05-20 enjoy-digitalMerge pull request #516 from antmicro/i2s_support_arty blob | commitdiff | raw | diff to current
2020-05-20 enjoy-digitalMerge pull request #534 from fjullien/fix_litex_sim_warn blob | commitdiff | raw | diff to current
2020-05-20 Franck Jullienlitex/sim: fix compiler warnings blob | commitdiff | raw | diff to current
2019-06-11 enjoy-digitalMerge pull request #198 from TomKeddie/tomk_20190610_ar... blob | commitdiff | raw | diff to current
2019-06-07 Florent Kermarrecbuild/sim: allow defining start/end cycles for tracing blob | commitdiff | raw | diff to current
2019-04-19 Sean CrossMerge branch 'master' of https://github.com/enjoy-digit... blob | commitdiff | raw | diff to current
2019-04-17 enjoy-digitalMerge pull request #162 from antmicro/full-conf-vexriscv blob | commitdiff | raw | diff to current
2019-04-17 enjoy-digitalMerge pull request #163 from gsomlo/gls-verilated-cmdargs blob | commitdiff | raw | diff to current
2019-04-17 Gabriel L. Somlobuild/sim/core: Initialize Verilator commandArgs blob | commitdiff | raw | diff to current
2018-12-20 Tim AnsellMerge pull request #144 from mithro/nextpnr-migen-update blob | commitdiff | raw | diff to current
2018-12-20 Florent Kermarrecbuild/sim: handle verilog $finish and if coverage is... blob | commitdiff | raw | diff to current
2017-06-28 Florent Kermarreclitex/build/sim: rename c functions from lambdasim... blob | commitdiff | raw | diff to current
2017-06-28 Pierre-Olivier Vauboinlitex/build/sim: introduce new simulator with modules... blob | commitdiff | raw | diff to current