svp64: align on 64-byte boundary
[binutils-gdb.git] / opcodes /
2024-02-29 Dmitry Selyutinppc-opc: sync instructions
2024-02-29 Dmitry Selyutinall: sync recent ff/pi/lf updates
2024-02-29 Dmitry Selyutinsvp64: mark RA0 operands; introduce RT0 operand
2024-02-29 Dmitry Selyutinppc: support binlog instructions
2024-02-29 Dmitry Selyutinppc: support ternlogi instructions
2024-02-29 Dmitry Selyutinppc: support ffadds instruction
2023-11-14 Dmitry Selyutinppc: support fdmadds instruction
2023-11-14 Dmitry Selyutinppc: support ffnmadds instruction
2023-11-14 Dmitry Selyutinppc: support ffnmsubs instruction
2023-11-14 Dmitry Selyutinppc: support ffmadds instruction
2023-11-14 Dmitry Selyutinppc: support ffmsubs instruction
2023-11-14 Dmitry Selyutinppc: support minmax aliases
2023-11-14 Dmitry Selyutinppc: support minmax instruction
2023-11-14 Dmitry Selyutinppc: support maddedus instruction
2023-11-14 Dmitry Selyutinppc: support dsrd instruction
2023-11-14 Dmitry Selyutinppc: support dsld instruction
2023-11-14 Dmitry Selyutinppc-opc.c: place new instructions at SFFS level
2023-11-14 Dmitry Selyutinsvp64: sync specifiers
2023-11-14 Dmitry Selyutinppc/svp64: support optional operands disassembly
2023-11-14 Dmitry Selyutinppc/svp64: disassemble branch mode
2023-11-14 Dmitry Selyutinppc/svp64: disassemble CR op mode
2023-11-14 Dmitry Selyutinppc/svp64: disassemble ld/st idx mode
2023-11-14 Dmitry Selyutinppc/svp64: disassemble ld/st imm mode
2023-11-14 Dmitry Selyutinppc/svp64: disassemble normal mode
2023-11-14 Dmitry Selyutinppc/svp64: disassemble SVP64 operands
2023-11-14 Dmitry Selyutinppc/svp64: disassemble SVP64 name
2023-11-14 Dmitry Selyutinppc/svp64: obtain SVP64 disassembly context
2023-11-14 Dmitry Selyutinppc/svp64: share SVP64 context via libopcodes
2023-11-14 Dmitry Selyutinppc/svp64: introduce SVP64 opcode lookup
2023-11-14 Dmitry Selyutinppc: decouple print_insn_powerpc_opcode routine
2023-11-14 Dmitry Selyutinopcodes: introduce SVP64 sources
2023-11-14 Dmitry Selyutinppc/svp64: support shadd/shadduw instructions
2023-11-14 Dmitry Selyutinppc/svp64: support divmod2du instruction
2023-11-14 Dmitry Selyutinppc/svp64: support maddedu instruction
2023-11-14 Dmitry Selyutinppc/svp64: support fptrans instructions
2023-11-14 Dmitry Selyutinppc/svp64: support bmask instruction
2023-11-14 Dmitry Selyutinppc/svp64: support absd instructions
2023-11-14 Dmitry Selyutinppc/svp64: support cprop instructions
2023-11-14 Dmitry Selyutinppc/svp64: support avgadd instructions
2023-11-14 Dmitry Selyutinppc/svp64: support fishmv instruction
2023-11-14 Dmitry Selyutinppc/svp64: support fmvis instruction
2023-11-14 Dmitry Selyutinppc/svp64: support svshape2 instruction
2023-11-14 Dmitry Selyutinppc: decouple SFFS and SVP64 extensions
2023-11-10 Lulu CaiAdd support for ilp32 register alias.
2023-11-09 Victor Do Nascimentoaarch64: Fix error in THE system register checking
2023-11-09 Jan Beulichx86: rework UWRMSR operand swapping
2023-11-09 Jan Beulichx86: do away with is_evex_encoding()
2023-11-09 Jan Beulichx86: split insn templates' CPU field
2023-11-09 Jan Beulichx86: Cpu64 handling improvements
2023-11-09 Jan Beulichx86: Intel Core processors do not support CMPXCHG16B
2023-11-07 Victor Do Nascimentoaarch64: Add LSE128 instructions
2023-11-07 Victor Do Nascimentoaarch64: Add arch support for LSE128 extension
2023-11-07 Victor Do Nascimentoaarch64: Add LSE128 instruction operand support
2023-11-07 Victor Do Nascimentoaarch64: Add 128-bit system register flags
2023-11-07 Victor Do Nascimentoaarch64: Add THE system register support
2023-11-07 Mary BennettRISC-V: Add support for XCValu extension in CV32E40P
2023-11-07 Mary BennettRISC-V: Add support for XCVmac extension in CV32E40P
2023-11-03 Jan BeulichRISC-V: reduce redundancy in load/store macro insn...
2023-11-02 Srinath Parvathaneniaarch64: Add GCS system registers.
2023-11-02 Srinath Parvathaneniaarch64: Add support for GCSB DSYNC instruction.
2023-11-02 srinathaarch64: Add support for GCS extension.
2023-11-02 Srinath Parvathaneniaarch64: Add support for Check Feature Status Extension.
2023-10-31 Hu, Lin1Support Intel USER_MSR
2023-10-30 Victor Do Nascimentoaarch64: Update aarch64-sys-regs.def header
2023-10-28 Jose E. Marchesiopcodes: bpf-dis.c: fix typo in comment
2023-10-20 Neal Frageropcodes: microblaze: Fix bit masking bug
2023-10-15 Neal Frageropcodes: microblaze: Add new bit-field instructions
2023-10-13 Joseph FaullsRISC-V: Add support for numbered ISA mapping strings
2023-10-07 Michael J. EagerRevert "opcodes: microblaze: Add new bit-field instruct...
2023-10-06 Neal Frageropcodes: microblaze: Add new bit-field instructions
2023-10-05 Neal fragermicroblaze: Add address extension instructions
2023-10-04 Neal frageropcodes: microblaze: Add hibernate and suspend instructions
2023-10-04 Victor Do Nascimentoaarch64: Refactor system register data
2023-10-04 Victor Do Nascimentoaarch64: system register aliasing detection
2023-09-27 Neal Frageropcodes: microblaze: Add wdc.ext.clear and wdc.ext...
2023-09-27 Jan Beulichx86: fold FMA VEX and EVEX templates
2023-09-27 Jan Beulichx86: fold VAES/VPCLMULQDQ VEX and EVEX templates
2023-09-27 Jan Beulichx86: fold certain VEX and EVEX templates
2023-09-27 mengqinggangAdd support for "pcaddi rd, symbol"
2023-09-26 Richard Sandifordaarch64: Restructure feature flag handling
2023-09-25 Claudiu ZissulescuRevert "arc: Add new opcode functions for ARCv3 ISA."
2023-09-25 Claudiu ZissulescuRevert "arc: New ARCv3 ISA instruction table"
2023-09-25 Claudiu Zissulescuarc: New ARCv3 ISA instruction table
2023-09-25 Claudiu Zissulescuarc: Add new opcode functions for ARCv3 ISA.
2023-09-15 Jan Beulichx86: fold CpuLM and Cpu64
2023-09-14 Jan Beulichx86: Vxy naming correction
2023-09-14 Jan Beulichx86: support AVX10.1 vector size restrictions
2023-09-14 Jan Beulichx86: support AVX10.1/512
2023-09-14 Jan Beulichx86: make AES/PCMULQDQ respectively prereqs of VAES...
2023-09-08 Vladimir MezentsevSet insn_type for branch instructions on aarch64
2023-09-07 Alan ModraPR30793, kvx_reassemble_bundle index 8 out of bounds
2023-09-07 Nelson ChuRISC-V: Clarify the naming rules of vendor operands.
2023-09-05 Jan BeulichRISC-V: fold duplicate code in vector_macro()
2023-09-01 Jan Beulichx86: rename CpuPCLMUL
2023-09-01 Jan Beulichx86: drop Size64 from VMOVQ
2023-09-01 Jan BeulichRISC-V: move various alias entries
2023-08-30 Tsukasa OIRISC-V: Make XVentanaCondOps RV64 only
2023-08-26 Tom TromeySimplify definition of GUILE
2023-08-26 Alan Modraopcodes i386 and ia64 gen file warnings
2023-08-24 Paul Iannettakvx: fix kvx_reassemble_bundle index 8 out of bounds
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