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soc/integration/csr_bridge: use registered version only when SDRAM is present.
[litex.git]
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test
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test_wishbone.py
2020-07-22
enjoy-digital
Merge pull request #599 from antmicro/gen-mmcm-pr
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2020-07-21
Florent Kermarrec
interconnect/wishbone: add minimal UpConverter.
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projects / litex.git / history