soc.git
3 years agoput sv_input_record_layout onto CompOpSubsetBase after all
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:38:39 +0000 (13:38 +0100)]
put sv_input_record_layout onto CompOpSubsetBase after all

3 years agowhoops wrong signal name, set exc_happened
Luke Kenneth Casson Leighton [Wed, 5 May 2021 12:38:11 +0000 (13:38 +0100)]
whoops wrong signal name, set exc_happened

3 years agoadd SVP64 RM fields to ALU input record
Luke Kenneth Casson Leighton [Wed, 5 May 2021 11:51:26 +0000 (12:51 +0100)]
add SVP64 RM fields to ALU input record

3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 4 May 2021 19:25:22 +0000 (21:25 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agoimplement MFSPR the same way as fu/spr/main_stage.py
Tobias Platen [Tue, 4 May 2021 19:23:32 +0000 (21:23 +0200)]
implement MFSPR the same way as fu/spr/main_stage.py

3 years agoremove minerva debug unit (not needed)
Luke Kenneth Casson Leighton [Tue, 4 May 2021 19:21:04 +0000 (20:21 +0100)]
remove minerva debug unit (not needed)

3 years agominerva tests: Don't import soc.minerva.csr
Jonathan Neuschäfer [Tue, 4 May 2021 11:09:49 +0000 (13:09 +0200)]
minerva tests: Don't import soc.minerva.csr

Fixes: 4af6717b ("remove unneeded minerva code")
3 years ago.gitlab-ci.yml: Silence pywriter harder
Jonathan Neuschäfer [Tue, 4 May 2021 08:03:17 +0000 (10:03 +0200)]
.gitlab-ci.yml: Silence pywriter harder

"make -j$(nproc) pywriter" and "pywriter" fill the log with over 20000
lines like this:

> /builds/neuschaefer/soc/openpower-isa/src/openpower/decoder/power_decoder.py:420: UnusedElaboratable: <openpower.decoder.power_decoder.PowerDecoder object at 0x7f4bf8ae8e48> created but never used
>   row_subset=self.row_subsetfn)
> UnusedElaboratable: Enable tracemalloc to get the object allocation traceback

Ideally, the relevant code should be fixed to avoid this warning, but for now,
I'm silencing it, so I can fit more relevant output into GitLab-CI's 4 MiB limit.

3 years ago.gitlab-ci.yml: Trim log output
Jonathan Neuschäfer [Tue, 4 May 2021 06:19:29 +0000 (08:19 +0200)]
.gitlab-ci.yml: Trim log output

GitLab-CI limits log output to 4 MiB, which the build job currently
exceeds. Trim the output of some of the earlier steps, to make it
possible to figure out what went wrong in the later steps.

3 years ago.gitlab-ci.yml: Fix invocation of pywriter
Jonathan Neuschäfer [Mon, 3 May 2021 21:14:35 +0000 (23:14 +0200)]
.gitlab-ci.yml: Fix invocation of pywriter

See ffb6288f ("svanalysis and pywriter now command-line scripts").

3 years ago.gitlab-ci.yml: Clone and build power-instruction-analyzer
Jonathan Neuschäfer [Tue, 4 May 2021 10:57:26 +0000 (12:57 +0200)]
.gitlab-ci.yml: Clone and build power-instruction-analyzer

3 years ago.gitlab-ci.yml: Clone and build c4m-jtag
Jonathan Neuschäfer [Tue, 4 May 2021 10:28:56 +0000 (12:28 +0200)]
.gitlab-ci.yml: Clone and build c4m-jtag

3 years ago.gitlab-ci.yml: Clone and build openpower-isa
Jonathan Neuschäfer [Mon, 3 May 2021 21:57:58 +0000 (23:57 +0200)]
.gitlab-ci.yml: Clone and build openpower-isa

3 years ago.gitlab-ci.yml: Install Rust and cargo
Jonathan Neuschäfer [Mon, 3 May 2021 20:33:12 +0000 (22:33 +0200)]
.gitlab-ci.yml: Install Rust and cargo

Unfortunately, Rust 1.41 (as available in Debian 10) is too old for
object v0.23.0, a dependency of maturin:

error[E0658]: subslice patterns are unstable
   --> /root/.cargo/registry/src/github.com-1ecc6299db9ec823/object-0.23.0/src/read/mod.rs:162:41
    |
162 |             [0x7f, b'E', b'L', b'F', 1, ..] => FileKind::Elf32,
    |                                         ^^
    |
    = note: for more information, see https://github.com/rust-lang/rust/issues/62254

... so we have to resort to rustup.

3 years ago.gitlab-ci.yml: Remove tags from nmigen-soc repo
Jonathan Neuschäfer [Mon, 3 May 2021 19:13:18 +0000 (21:13 +0200)]
.gitlab-ci.yml: Remove tags from nmigen-soc repo

In nmigen-soc, setuptools complains:

  pkg_resources.extern.packaging.version.InvalidVersion: Invalid version: '24jan2021_ls180'

This commit is partially inspired by: https://git.libre-soc.org/?p=dev-env-setup.git;a=commitdiff;h=6b79a0fea2052a8b35a4f130a64c119983d40f3c

3 years ago.gitlab-ci.yml: Rewrite git://git.libre-riscv.org URLs to https://git.libre-soc.org/
Jonathan Neuschäfer [Mon, 3 May 2021 19:01:02 +0000 (21:01 +0200)]
.gitlab-ci.yml: Rewrite git://git.libre-riscv.org URLs to https://git.libre-soc.org/

git.libre-soc.org supports git over HTTPS, so let's use it.

3 years agowhoops disabled some test_issuer group tests
Luke Kenneth Casson Leighton [Tue, 4 May 2021 18:33:34 +0000 (19:33 +0100)]
whoops disabled some test_issuer group tests

3 years agoadd SVSTATE (SVSRR0) to TRAP pipeline
Luke Kenneth Casson Leighton [Tue, 4 May 2021 17:40:35 +0000 (18:40 +0100)]
add SVSTATE (SVSRR0) to TRAP pipeline
involves adding svstate to TrapOutputData regspec, and a corresponding
write port to StateRegs, and adding svstate to CompTrapOpSubset

3 years agoupate dsisr and dar using sync
Tobias Platen [Tue, 4 May 2021 18:32:39 +0000 (20:32 +0200)]
upate dsisr and dar using sync

3 years agoadding fast3 SPR to Trap pipeline and unit test
Luke Kenneth Casson Leighton [Tue, 4 May 2021 17:09:36 +0000 (18:09 +0100)]
adding fast3 SPR to Trap pipeline and unit test

3 years agonew fast3 needs to be remapped to fast1 port in "reduced ports" case in core
Luke Kenneth Casson Leighton [Tue, 4 May 2021 17:08:56 +0000 (18:08 +0100)]
new fast3 needs to be remapped to fast1 port in "reduced ports" case in core

3 years agomissed that soc.regfile.util has moved to openpower.util
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:32:40 +0000 (17:32 +0100)]
missed that soc.regfile.util has moved to openpower.util

3 years agoadd SVSRR0 to FastRegsEnum
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:32:26 +0000 (17:32 +0100)]
add SVSRR0 to FastRegsEnum

3 years agoadd TODO comments and cross-reference to bug
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:18:33 +0000 (17:18 +0100)]
add TODO comments and cross-reference to bug
https://bugs.libre-soc.org/show_bug.cgi?id=636
TestIssuer EXECUTE_WAIT FSM needs to note that an exception has happened
and *re-execute* the instruction

3 years agonote a way to see if an exception happened, in TestIssuer
Luke Kenneth Casson Leighton [Tue, 4 May 2021 16:02:49 +0000 (17:02 +0100)]
note a way to see if an exception happened, in TestIssuer

3 years agoadd printout showing exception output from FUs
Luke Kenneth Casson Leighton [Tue, 4 May 2021 15:56:06 +0000 (16:56 +0100)]
add printout showing exception output from FUs

3 years agoremove symlink
Luke Kenneth Casson Leighton [Tue, 4 May 2021 14:44:39 +0000 (15:44 +0100)]
remove symlink

3 years agoadd links in README
Luke Kenneth Casson Leighton [Tue, 4 May 2021 14:39:10 +0000 (15:39 +0100)]
add links in README

3 years agomore rename of exception_o to exc_o, add convenience function in TestCore
Luke Kenneth Casson Leighton [Tue, 4 May 2021 14:18:51 +0000 (15:18 +0100)]
more rename of exception_o to exc_o, add convenience function in TestCore
to get at all exceptions

3 years agowire in exc_o.happened into write-cancellation of LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 4 May 2021 14:18:08 +0000 (15:18 +0100)]
wire in exc_o.happened into write-cancellation of LDSTCompUnit

3 years agocomments, and change name of LDSTCompUnit exception_o to exc_o
Luke Kenneth Casson Leighton [Tue, 4 May 2021 13:55:14 +0000 (14:55 +0100)]
comments, and change name of LDSTCompUnit exception_o to exc_o

3 years agoremove exception from data on FUBaseData, explicitly eq() it
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:55:57 +0000 (13:55 +0100)]
remove exception from data on FUBaseData, explicitly eq() it

3 years agocode-comments for LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:41:14 +0000 (13:41 +0100)]
code-comments for LDSTCompUnit

3 years agoadd LDSTException class to LDSTOutputData
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:35:54 +0000 (13:35 +0100)]
add LDSTException class to LDSTOutputData

3 years agoadd option to add exception type to FUBaseData (pipe_data)
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:31:35 +0000 (13:31 +0100)]
add option to add exception type to FUBaseData (pipe_data)

3 years agorename IntegerData to FUBaseData
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:25:30 +0000 (13:25 +0100)]
rename IntegerData to FUBaseData

3 years agocomment out nc (nocache), it seems to actually work
Luke Kenneth Casson Leighton [Tue, 4 May 2021 12:24:30 +0000 (13:24 +0100)]
comment out nc (nocache), it seems to actually work

3 years agoMMU: get store to activate only when data is available, and to wait till done
Luke Kenneth Casson Leighton [Mon, 3 May 2021 15:28:14 +0000 (16:28 +0100)]
MMU: get store to activate only when data is available, and to wait till done

3 years agodisable the cache for now, whilst testing read/write corruption
Luke Kenneth Casson Leighton [Mon, 3 May 2021 15:05:54 +0000 (16:05 +0100)]
disable the cache for now, whilst testing read/write corruption

3 years agouse Const to define bit-length when comparing top nibble of address in MMU
Luke Kenneth Casson Leighton [Sun, 2 May 2021 20:05:48 +0000 (21:05 +0100)]
use Const to define bit-length when comparing top nibble of address in MMU

3 years agommu FSM store in dcache: only put data onto d_in on write request
Luke Kenneth Casson Leighton [Sun, 2 May 2021 19:55:26 +0000 (20:55 +0100)]
mmu FSM store in dcache: only put data onto d_in on write request

3 years agoreturn d_out.valid instead of always "ok" in MMU FSM
Luke Kenneth Casson Leighton [Sun, 2 May 2021 14:38:37 +0000 (15:38 +0100)]
return d_out.valid instead of always "ok" in MMU FSM

3 years agoHACK WARNING: disable d-cache on hard-coded address 0xCxxx_xxxx
Luke Kenneth Casson Leighton [Sun, 2 May 2021 14:21:21 +0000 (15:21 +0100)]
HACK WARNING: disable d-cache on hard-coded address 0xCxxx_xxxx
this is for peripherals

3 years agoadd nc argument to dcache load/store tests
Luke Kenneth Casson Leighton [Sun, 2 May 2021 14:20:18 +0000 (15:20 +0100)]
add nc argument to dcache load/store tests

3 years agoquick hack to SRAM test and to dcache to enable classic wishbone
Luke Kenneth Casson Leighton [Sun, 2 May 2021 10:39:48 +0000 (11:39 +0100)]
quick hack to SRAM test and to dcache to enable classic wishbone

3 years agoadjust dependencies in setup.py
Luke Kenneth Casson Leighton [Sun, 2 May 2021 05:55:06 +0000 (06:55 +0100)]
adjust dependencies in setup.py

3 years agoenable issuer_verilog.py to generate new MMU/DCache config memory type
Luke Kenneth Casson Leighton [Sat, 1 May 2021 20:47:27 +0000 (21:47 +0100)]
enable issuer_verilog.py to generate new MMU/DCache config memory type

3 years agosend a DMI RESET at the end of the test.
Luke Kenneth Casson Leighton [Sat, 1 May 2021 20:45:16 +0000 (21:45 +0100)]
send a DMI RESET at the end of the test.
this resets DCache otherwise it contains old values from the previous test

3 years agostore data in microwatt dcache goes in one cycle AFTER valid is set
Luke Kenneth Casson Leighton [Sat, 1 May 2021 19:31:08 +0000 (20:31 +0100)]
store data in microwatt dcache goes in one cycle AFTER valid is set

3 years agodcache store test: data goes in one cycle AFTER valid/addr set up
Luke Kenneth Casson Leighton [Sat, 1 May 2021 19:28:31 +0000 (20:28 +0100)]
dcache store test: data goes in one cycle AFTER valid/addr set up

3 years agoonly do dcache lookup for now
Luke Kenneth Casson Leighton [Sat, 1 May 2021 19:08:23 +0000 (20:08 +0100)]
only do dcache lookup for now

3 years agoAdd GTKWave documents to each DCache unit test
Cesar Strauss [Sat, 1 May 2021 19:04:19 +0000 (16:04 -0300)]
Add GTKWave documents to each DCache unit test

3 years agoadd LD/ST cases to MMU, which should all still work
Luke Kenneth Casson Leighton [Sat, 1 May 2021 16:39:53 +0000 (17:39 +0100)]
add LD/ST cases to MMU, which should all still work

3 years agoadd MMUTestCaseROM
Luke Kenneth Casson Leighton [Sat, 1 May 2021 15:24:49 +0000 (16:24 +0100)]
add MMUTestCaseROM

3 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 1 May 2021 15:13:01 +0000 (16:13 +0100)]
whitespace

3 years agouse new AllFunctionUnits.get_fu function
Luke Kenneth Casson Leighton [Sat, 1 May 2021 13:16:20 +0000 (14:16 +0100)]
use new AllFunctionUnits.get_fu function

3 years agouse SPRreduced to match PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 1 May 2021 13:15:10 +0000 (14:15 +0100)]
use SPRreduced to match PowerDecoder2
extend mmu_sprs to include redirection of PRTBL DSISR DAR and PIDR to MMU

3 years agomissing self.
Luke Kenneth Casson Leighton [Sat, 1 May 2021 12:22:30 +0000 (13:22 +0100)]
missing self.

3 years agoresolve DriverConflict in TstL0CacheBuffer, really bad hack
Luke Kenneth Casson Leighton [Sat, 1 May 2021 12:13:00 +0000 (13:13 +0100)]
resolve DriverConflict in TstL0CacheBuffer, really bad hack

3 years agodebug and stop on mmu test_pipe_caller.py
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 15:25:20 +0000 (16:25 +0100)]
debug and stop on mmu test_pipe_caller.py

3 years agocomments on dcache-to-mmu link
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 15:25:05 +0000 (16:25 +0100)]
comments on dcache-to-mmu link

3 years agoadd a TestSRAM variant of LoadStore1, for being able to run unit MMU unit tests
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 14:23:34 +0000 (15:23 +0100)]
add a TestSRAM variant of LoadStore1, for being able to run unit MMU unit tests

3 years agoadd basic test_issuer_mmu.py
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 13:09:17 +0000 (14:09 +0100)]
add basic test_issuer_mmu.py
for running specifically with microwatt_mmu=True

3 years agoadd option to use new mmu_cache_wb ConfigMemoryPortInterface
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 13:05:01 +0000 (14:05 +0100)]
add option to use new mmu_cache_wb ConfigMemoryPortInterface

3 years agohook up dcache wb_in/out to PortInterfaceBase Wishbone Record
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 12:48:34 +0000 (13:48 +0100)]
hook up dcache wb_in/out to PortInterfaceBase Wishbone Record

3 years agosort out spblock 4k sram cell instance name to match coriolis2 changes
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 11:46:50 +0000 (12:46 +0100)]
sort out spblock 4k sram cell instance name to match coriolis2 changes

3 years agohttps://bugs.libre-soc.org/show_bug.cgi?id=635
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 10:23:57 +0000 (11:23 +0100)]
https://bugs.libre-soc.org/show_bug.cgi?id=635
turned out to be as simple as the test infrastructure setting initial
values in the wrong regfile (only a few of the unit tests set initial
values in SPR regfiles)

3 years agobetter reporting on gpr comparisons
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 10:19:28 +0000 (11:19 +0100)]
better reporting on gpr comparisons

3 years agoset up LoadStore1 in ConfigMemoryPortInterface and hook it up in MMU
Luke Kenneth Casson Leighton [Fri, 30 Apr 2021 00:22:21 +0000 (01:22 +0100)]
set up LoadStore1 in ConfigMemoryPortInterface and hook it up in MMU

3 years agocomment out adding mmu and dcache to pspec in MMU FSM
Luke Kenneth Casson Leighton [Thu, 29 Apr 2021 22:00:52 +0000 (23:00 +0100)]
comment out adding mmu and dcache to pspec in MMU FSM

3 years agomove dcache into Loadstore1
Luke Kenneth Casson Leighton [Thu, 29 Apr 2021 21:58:31 +0000 (22:58 +0100)]
move dcache into Loadstore1

3 years agoadd option to disable bus forwarding on SPRs and FAST regs.
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 18:51:02 +0000 (19:51 +0100)]
add option to disable bus forwarding on SPRs and FAST regs.
not StateRegs: that actually critically depends on access to PC through
bus forwarding

3 years agoadd option to enable/disable bus forwarding mode on INT regfile
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 18:46:57 +0000 (19:46 +0100)]
add option to enable/disable bus forwarding mode on INT regfile

3 years agoreturn read data out from Loadstore1 only when valid
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 18:46:24 +0000 (19:46 +0100)]
return read data out from Loadstore1 only when valid

3 years agohook up MSR into MMU (TODO, use a lot less bits)
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 20:45:10 +0000 (21:45 +0100)]
hook up MSR into MMU (TODO, use a lot less bits)

3 years agosimple regression dcache test was faulty. wishbone pipeline related
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 20:23:39 +0000 (21:23 +0100)]
simple regression dcache test was faulty.  wishbone pipeline related

3 years agocomment read ack in sram
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 09:32:42 +0000 (10:32 +0100)]
comment read ack in sram

3 years agoincorrect indentation in dcache rams
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 09:19:26 +0000 (10:19 +0100)]
incorrect indentation in dcache rams

3 years agosimplify dcache test
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 08:22:14 +0000 (09:22 +0100)]
simplify dcache test

3 years agospelling mistake
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 22:51:07 +0000 (23:51 +0100)]
spelling mistake

3 years agoremove RegStage1.real_adr temporary from dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 22:17:09 +0000 (23:17 +0100)]
remove RegStage1.real_adr temporary from dcache

3 years agodo not overwrite parameter ra in dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 22:03:05 +0000 (23:03 +0100)]
do not overwrite parameter ra in dcache

3 years agocomment out dcache_store from test, not the problem
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 21:22:49 +0000 (22:22 +0100)]
comment out dcache_store from test, not the problem

3 years agoremove unneeded code
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 21:02:01 +0000 (22:02 +0100)]
remove unneeded code

3 years agoread req in wb_in.stall, dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 20:35:22 +0000 (21:35 +0100)]
read req in wb_in.stall, dcache

3 years agoShift-out skipped mask bits for both crpred and intpred
Cesar Strauss [Sun, 25 Apr 2021 19:11:19 +0000 (16:11 -0300)]
Shift-out skipped mask bits for both crpred and intpred

If src/dest step are not zero, we need to shift-out the skipped mask
bits. We already did this for intpred, and for crpred it's exactly the
same.
Move the shifting logic to a new last state, commonly used for both
intpred and crpred.

3 years agoadd single regression test for dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 20:15:56 +0000 (21:15 +0100)]
add single regression test for dcache

3 years agoadd TODO comment in dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 10:55:31 +0000 (11:55 +0100)]
add TODO comment in dcache

3 years agomove Signals in dcache to relevant context
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 10:46:50 +0000 (11:46 +0100)]
move Signals in dcache to relevant context

3 years agodcache Elif used where If should have been
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 10:43:35 +0000 (11:43 +0100)]
dcache Elif used where If should have been

3 years agowhoops should be cyc & ~ack
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 08:52:22 +0000 (09:52 +0100)]
whoops should be cyc & ~ack

3 years agohard-code dcache stall signal to non-pipelined mode
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 08:39:56 +0000 (09:39 +0100)]
hard-code dcache stall signal to non-pipelined mode

3 years agoincrease memory size in dcache test
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:26:32 +0000 (21:26 +0100)]
increase memory size in dcache test

3 years agoincrease size of random dcache testing by 10
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:18:18 +0000 (21:18 +0100)]
increase size of random dcache testing by 10

3 years agofix errors in dcache unit test
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:10:39 +0000 (21:10 +0100)]
fix errors in dcache unit test

3 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:10:27 +0000 (21:10 +0100)]
whitespace

3 years agoadd additional external libre-soc sphinx references... commented out for now
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:36:49 +0000 (16:36 +0100)]
add additional external libre-soc sphinx references... commented out for now

3 years agoadd additional external libre-soc sphinx references
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:36:26 +0000 (16:36 +0100)]
add additional external libre-soc sphinx references

3 years agoremove code moved to openpower-isa repo
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 10:51:24 +0000 (11:51 +0100)]
remove code moved to openpower-isa repo

3 years agoadd comments on TestIssuer TestRunner
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 22:17:11 +0000 (23:17 +0100)]
add comments on TestIssuer TestRunner