soc.git
3 years agoadd sld test with RB=64 to see what happens
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 23:48:23 +0000 (00:48 +0100)]
add sld test with RB=64 to see what happens

3 years agoreduce CSR data width to 8 as an experiment
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 23:48:08 +0000 (00:48 +0100)]
reduce CSR data width to 8 as an experiment

3 years agoadd UART reserved IRQ @ 0
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 19:56:44 +0000 (20:56 +0100)]
add UART reserved IRQ @ 0

3 years agoadd XICS memory regions, shrink litex CSR memmap size to do it
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 19:48:30 +0000 (20:48 +0100)]
add XICS memory regions, shrink litex CSR memmap size to do it

3 years agoadding XICS wb slave devices to litex sim
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 19:03:02 +0000 (20:03 +0100)]
adding XICS wb slave devices to litex sim
also linking external interrupt line

3 years agobring out XICS ICS interrupt levels so that they can be wired to peripherals
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 15:16:40 +0000 (16:16 +0100)]
bring out XICS ICS interrupt levels so that they can be wired to peripherals

3 years agoadding option to include XICS external interrupts.
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 15:11:10 +0000 (16:11 +0100)]
adding option to include XICS external interrupts.
XICS ICP and ICS are included, the wishbone slave ports added to TestIssuer
then if ext_irq is raised in core, execution jumps to 0x500 through a TRAP

3 years agoadd means to run hello_world.bin under simulation
Luke Kenneth Casson Leighton [Fri, 4 Sep 2020 12:01:09 +0000 (13:01 +0100)]
add means to run hello_world.bin under simulation
works with both microwatt and libresoc

3 years agoupdate to match refactored power-instruction-analyzer API
Jacob Lifshay [Fri, 4 Sep 2020 04:32:56 +0000 (21:32 -0700)]
update to match refactored power-instruction-analyzer API

matches the api of power-instruction-analyzer commit e828d2acecc25a82d5c29b765163a10993547566

3 years agoProvide full name and email in copyright notice.
Samuel A. Falvo II [Thu, 3 Sep 2020 22:12:58 +0000 (15:12 -0700)]
Provide full name and email in copyright notice.

3 years agodo more on dcache conversion
Luke Kenneth Casson Leighton [Thu, 3 Sep 2020 19:29:21 +0000 (20:29 +0100)]
do more on dcache conversion

3 years agotesting microwatt 3.bin (2.bin ok)
Luke Kenneth Casson Leighton [Thu, 3 Sep 2020 07:45:23 +0000 (08:45 +0100)]
testing microwatt 3.bin (2.bin ok)

3 years agowhen mtocrf FXM is 0, the CR has to be set to CR7
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 22:08:27 +0000 (23:08 +0100)]
when mtocrf FXM is 0, the CR has to be set to CR7

3 years agofix bug in cmpli (and cmplw)
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 17:48:34 +0000 (18:48 +0100)]
fix bug in cmpli (and cmplw)

3 years agosign-extend lhax needs 16-64, separate from lwax which is 32-64
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 16:48:17 +0000 (17:48 +0100)]
sign-extend lhax needs 16-64, separate from lwax which is 32-64

3 years agoadd bc ctr regression test when CTR=0 and CTR=1
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 16:38:03 +0000 (17:38 +0100)]
add bc ctr regression test when CTR=0 and CTR=1

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 14:13:31 +0000 (15:13 +0100)]
update submodule

3 years agobug in carry32 handling in OP_CMP
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 14:13:22 +0000 (15:13 +0100)]
bug in carry32 handling in OP_CMP

3 years agoadd cmpl regression test (one binary, one assembly)
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 14:13:06 +0000 (15:13 +0100)]
add cmpl regression test (one binary, one assembly)

3 years agoadd cmpl microwatt 1.bin test, cmpl
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 11:44:15 +0000 (12:44 +0100)]
add cmpl microwatt 1.bin test, cmpl

3 years agoseries of extensive modifications to fix long-standing bug in CR handling
Luke Kenneth Casson Leighton [Wed, 2 Sep 2020 11:32:38 +0000 (12:32 +0100)]
series of extensive modifications to fix long-standing bug in CR handling
cr as a FieldSelectableInt is being removed

3 years agoadd XER to fastregs and "construct" it in mfspr/mtspr
Luke Kenneth Casson Leighton [Mon, 31 Aug 2020 11:06:24 +0000 (12:06 +0100)]
add XER to fastregs and "construct" it in mfspr/mtspr

3 years agoredo OP_CMP based on microwatt. L=1 had been ignored
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 19:49:58 +0000 (20:49 +0100)]
redo OP_CMP based on microwatt.  L=1 had been ignored

3 years agoreversal of FXM mask for one-hot selection in OP_MTCR decode
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 14:45:03 +0000 (15:45 +0100)]
reversal of FXM mask for one-hot selection in OP_MTCR decode

3 years agoworking on dcache.py
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 12:05:36 +0000 (13:05 +0100)]
working on dcache.py

3 years agotidyup on mul proof
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 10:00:37 +0000 (11:00 +0100)]
tidyup on mul proof

3 years agoset mul post_stage o.ok only when needed, and fix xer_so pass-through
Luke Kenneth Casson Leighton [Sun, 30 Aug 2020 09:51:30 +0000 (10:51 +0100)]
set mul post_stage o.ok only when needed, and fix xer_so pass-through
https://bugs.libre-soc.org/show_bug.cgi?id=482

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sun, 30 Aug 2020 03:24:22 +0000 (20:24 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agoicache.py commit progress, about a third through the process
Cole Poirier [Sun, 30 Aug 2020 03:23:18 +0000 (20:23 -0700)]
icache.py commit progress, about a third through the process

3 years agoQualify XER_OV output in proof
Samuel A. Falvo II [Sat, 29 Aug 2020 23:53:49 +0000 (16:53 -0700)]
Qualify XER_OV output in proof

3 years agoFix test breakage in MUL proofs
Samuel A. Falvo II [Sat, 29 Aug 2020 23:27:54 +0000 (16:27 -0700)]
Fix test breakage in MUL proofs

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Sat, 29 Aug 2020 22:58:31 +0000 (15:58 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agommu.py, dcache.py, mem_types.py change types capitalization because I
Cole Poirier [Sat, 29 Aug 2020 22:56:15 +0000 (15:56 -0700)]
mmu.py, dcache.py, mem_types.py change types capitalization because I
was making typing errors, and this make more sense. Mmu -> MMU, Dcache
-> DCache, Icache -> ICache

3 years agomem_types add more types from common.vhdl specifially for icache,
Cole Poirier [Sat, 29 Aug 2020 22:41:07 +0000 (15:41 -0700)]
mem_types add more types from common.vhdl specifially for icache,
Fetch1ToIcacheType() and IcacheToDecode1Type()

3 years agomem_types.py arrange in alphabetical order for ease of reference, align
Cole Poirier [Sat, 29 Aug 2020 22:32:38 +0000 (15:32 -0700)]
mem_types.py arrange in alphabetical order for ease of reference, align
formatting

3 years agoBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!
Samuel A. Falvo II [Sat, 29 Aug 2020 22:24:15 +0000 (15:24 -0700)]
BROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!

3 years agommu.py remove duplicate comment left over from mmu.vhdl
Cole Poirier [Sat, 29 Aug 2020 22:06:01 +0000 (15:06 -0700)]
mmu.py remove duplicate comment left over from mmu.vhdl

3 years agoicache.py initial commit of first attempt at translation of icache.vhdl
Cole Poirier [Sat, 29 Aug 2020 22:02:56 +0000 (15:02 -0700)]
icache.py initial commit of first attempt at translation of icache.vhdl

3 years agoMove new write_gtkw and its example to nmutil
Cesar Strauss [Fri, 28 Aug 2020 09:55:10 +0000 (06:55 -0300)]
Move new write_gtkw and its example to nmutil

But keep using it to generate the GTKWave document for this unit test.

3 years agominor code-shuffle, comments
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 19:56:29 +0000 (20:56 +0100)]
minor code-shuffle, comments

3 years agoslowly morphing towards using an XER bit-field selector in decoder
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 19:42:35 +0000 (20:42 +0100)]
slowly morphing towards using an XER bit-field selector in decoder

3 years agoMUL pipeline formal proofs complete, I *think*.
Samuel A. Falvo II [Sat, 29 Aug 2020 19:41:30 +0000 (12:41 -0700)]
MUL pipeline formal proofs complete, I *think*.

3 years agobreak down XER into flags
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 18:54:23 +0000 (19:54 +0100)]
break down XER into flags

3 years agoadd XER read via DMI interface to sim.py
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 18:47:40 +0000 (19:47 +0100)]
add XER read via DMI interface to sim.py

3 years agoadd hack to get at XER through DMI interface
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 18:41:49 +0000 (19:41 +0100)]
add hack to get at XER through DMI interface

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 18:29:16 +0000 (19:29 +0100)]
submodule update

3 years agoWIP: prep for 64-bit insns
Samuel A. Falvo II [Sat, 29 Aug 2020 17:28:12 +0000 (10:28 -0700)]
WIP: prep for 64-bit insns

3 years agoyep disable OE for MULH64/32 and EXTS and CNTZ
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 16:18:10 +0000 (17:18 +0100)]
yep disable OE for MULH64/32 and EXTS and CNTZ

3 years agoinvestigating CR mtocrf / mfocrf
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 15:27:23 +0000 (16:27 +0100)]
investigating CR mtocrf / mfocrf

3 years agoadd additional CR regression tests
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 13:19:48 +0000 (14:19 +0100)]
add additional CR regression tests

3 years agoallow pseudocode numbering to decrement in for-loops
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 13:19:11 +0000 (14:19 +0100)]
allow pseudocode numbering to decrement in for-loops

3 years agoadd wat to write out raw binary assembled programs
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 13:18:41 +0000 (14:18 +0100)]
add wat to write out raw binary assembled programs

3 years agoCR FXM becomes a full mask.
Luke Kenneth Casson Leighton [Sat, 29 Aug 2020 09:56:02 +0000 (10:56 +0100)]
CR FXM becomes a full mask.
https://bugs.libre-soc.org/show_bug.cgi?id=478

3 years agodcache.py add first attempt at translation of dcache_tb.vhdl as
Cole Poirier [Fri, 28 Aug 2020 03:04:55 +0000 (20:04 -0700)]
dcache.py add first attempt at translation of dcache_tb.vhdl as
dcache_sim()

3 years agodcache.py add skeleton sim and test adapted from mmu.py which was
Cole Poirier [Thu, 27 Aug 2020 23:38:09 +0000 (16:38 -0700)]
dcache.py add skeleton sim and test adapted from mmu.py which was
adapted from regfile.py

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Thu, 27 Aug 2020 23:35:21 +0000 (16:35 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agodcache.py implement the remaining vhdl generate statements in nmigen,
Cole Poirier [Thu, 27 Aug 2020 23:33:58 +0000 (16:33 -0700)]
dcache.py implement the remaining vhdl generate statements in nmigen,
fix formatting, typos

3 years agohttps://bugs.libre-soc.org/show_bug.cgi?id=476
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 20:18:12 +0000 (21:18 +0100)]
https://bugs.libre-soc.org/show_bug.cgi?id=476
XER SO not being "listened" to correctly when OE=0 and Rc=1 creating CR0

3 years agoxer so is not being passed through to CR0
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 19:52:58 +0000 (20:52 +0100)]
xer so is not being passed through to CR0

3 years agoreally bad hack to fix simulator bug in carry handling
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 19:37:04 +0000 (20:37 +0100)]
really bad hack to fix simulator bug in carry handling
https://bugs.libre-soc.org/show_bug.cgi?id=476

3 years agoaugment addme test case to show bug #476
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 17:20:29 +0000 (18:20 +0100)]
augment addme test case to show bug #476
https://bugs.libre-soc.org/show_bug.cgi?id=476

3 years agoadd addze and addme uni tests
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 16:23:17 +0000 (17:23 +0100)]
add addze and addme uni tests

3 years agoincompatibility with POWER9 on mulhw/u due to lack of spec clarity
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 16:23:01 +0000 (17:23 +0100)]
incompatibility with POWER9 on mulhw/u due to lack of spec clarity
both microwatt and IBM POWER9 violate spec
http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html

3 years agooverflow-enable does not occur on shift operations
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 14:20:31 +0000 (15:20 +0100)]
overflow-enable does not occur on shift operations

3 years agooink, write_cr shiftrot record width was zero (??)
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 14:01:23 +0000 (15:01 +0100)]
oink, write_cr shiftrot record width was zero (??)

3 years agosorting out shift_rot to use new output stage data structures
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 13:58:25 +0000 (14:58 +0100)]
sorting out shift_rot to use new output stage data structures
shift_rot does not modify OV/32 so needs its own output stage
similar to logical, SO is never set but is "read"

3 years agoneed to read SO if Rc=1
Luke Kenneth Casson Leighton [Thu, 27 Aug 2020 12:23:04 +0000 (13:23 +0100)]
need to read SO if Rc=1

3 years agoreorg of SO handling related to CR0
Luke Kenneth Casson Leighton [Wed, 26 Aug 2020 17:59:47 +0000 (18:59 +0100)]
reorg of SO handling related to CR0
because CR0 needs XER SO, logical pipe needs to read but not write SO
this means quite a substantial but relatively straightforward change
in the pipe_data for logical and ALU

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Wed, 26 Aug 2020 18:06:12 +0000 (11:06 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agodcache.py replace subtypes/types/constant aliases with the names of the
Cole Poirier [Wed, 26 Aug 2020 18:04:45 +0000 (11:04 -0700)]
dcache.py replace subtypes/types/constant aliases with the names of the
orignal constants that these were aliases of, tidy up
names

3 years agouse sub-test in logical test_pipe_caller
Luke Kenneth Casson Leighton [Wed, 26 Aug 2020 14:37:22 +0000 (15:37 +0100)]
use sub-test in logical test_pipe_caller

3 years agoinvestigating div fsm and simulator bug
Luke Kenneth Casson Leighton [Wed, 26 Aug 2020 14:29:01 +0000 (15:29 +0100)]
investigating div fsm and simulator bug

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Tue, 25 Aug 2020 20:35:04 +0000 (13:35 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agodcache.py rearrange, transform classes into functions with input
Cole Poirier [Tue, 25 Aug 2020 20:33:17 +0000 (13:33 -0700)]
dcache.py rearrange, transform classes into functions with input
parameters, fix typos, whitespace, syntax

3 years agofix broken remainder for div FSM
Jacob Lifshay [Tue, 25 Aug 2020 18:54:51 +0000 (11:54 -0700)]
fix broken remainder for div FSM

3 years agoclean up formatting
Jacob Lifshay [Tue, 25 Aug 2020 18:16:03 +0000 (11:16 -0700)]
clean up formatting

3 years agoalthough shift-rot does not alter XER.so it still needs it as input for CR0
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 13:30:04 +0000 (14:30 +0100)]
although shift-rot does not alter XER.so it still needs it as input for CR0

3 years agoadd way to capture CR from DMI in litex sim
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 11:59:38 +0000 (12:59 +0100)]
add way to capture CR from DMI in litex sim

3 years agoadd CR read to DMI interface
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 11:26:19 +0000 (12:26 +0100)]
add CR read to DMI interface

3 years agoshorten using temp vars
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 10:56:36 +0000 (11:56 +0100)]
shorten using temp vars

3 years agoadd CR DMI interface
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 10:54:35 +0000 (11:54 +0100)]
add CR DMI interface

3 years agoadd crxor unit test to qemu
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 10:52:24 +0000 (11:52 +0100)]
add crxor unit test to qemu

3 years agodcache.py fix whitespace, fomatting, syntax
Cole Poirier [Tue, 25 Aug 2020 01:19:24 +0000 (18:19 -0700)]
dcache.py fix whitespace, fomatting, syntax

3 years agodcache.py fix formatting
Cole Poirier [Tue, 25 Aug 2020 01:03:14 +0000 (18:03 -0700)]
dcache.py fix formatting

3 years agodcache.py move Reservation RecordObject to top of file
Cole Poirier [Tue, 25 Aug 2020 01:01:36 +0000 (18:01 -0700)]
dcache.py move Reservation RecordObject to top of file

3 years agodcache.py move RegStage1 RecordObject to top of file
Cole Poirier [Tue, 25 Aug 2020 00:59:16 +0000 (17:59 -0700)]
dcache.py move RegStage1 RecordObject to top of file

3 years agodcache.py move MemAccessRequest RecordObject to top of file, small
Cole Poirier [Tue, 25 Aug 2020 00:47:41 +0000 (17:47 -0700)]
dcache.py move MemAccessRequest RecordObject to top of file, small
formatting changes

3 years agodcache.py move Stage0 RecordObject to top of file
Cole Poirier [Tue, 25 Aug 2020 00:40:19 +0000 (17:40 -0700)]
dcache.py move Stage0 RecordObject to top of file

3 years agoargh, reading regfile over DMI was overlapped and corrupting reg 0
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 22:27:02 +0000 (23:27 +0100)]
argh, reading regfile over DMI was overlapped and corrupting reg 0

3 years agoadd isel CR tests to run on qemu (confirmed working)
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 18:45:13 +0000 (19:45 +0100)]
add isel CR tests to run on qemu (confirmed working)

3 years agoTestCachedMemoryPortInterface cleanup
Tobias Platen [Mon, 24 Aug 2020 16:50:47 +0000 (18:50 +0200)]
TestCachedMemoryPortInterface cleanup

3 years agomake it easier to select FSM/Pipe DIV unit
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 14:32:02 +0000 (15:32 +0100)]
make it easier to select FSM/Pipe DIV unit

3 years agofix *another* ld-update-related timing / FSM issue
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 14:04:55 +0000 (15:04 +0100)]
fix *another* ld-update-related timing / FSM issue

3 years agotidyup / shuffle after review
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 12:42:03 +0000 (13:42 +0100)]
tidyup / shuffle after review

3 years agoremove default parameter
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 12:30:28 +0000 (13:30 +0100)]
remove default parameter

3 years ago"WAY" does not exist - range(NUM_WAYS) was intended
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 11:43:34 +0000 (12:43 +0100)]
"WAY" does not exist - range(NUM_WAYS) was intended

3 years agouse WAY_BITS in appropriate locations
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 11:37:32 +0000 (12:37 +0100)]
use WAY_BITS in appropriate locations

3 years agoreminder that the license (reflecting what is in setup.py) is the LGPLv3
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 11:18:04 +0000 (12:18 +0100)]
reminder that the license (reflecting what is in setup.py) is the LGPLv3

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Mon, 24 Aug 2020 00:48:16 +0000 (17:48 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agodcache.py commit first full tranlation pass, about five percent left
Cole Poirier [Mon, 24 Aug 2020 00:46:21 +0000 (17:46 -0700)]
dcache.py commit first full tranlation pass, about five percent left
undone as I don't understand how to do it and need help