From 4a1ce4a397809a935d4ac79d02115a8d973dfec1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 26 Jun 2022 12:11:42 +0100 Subject: [PATCH] reduce icache/dcache TLB sizes --- src/soc/experiment/dcache.py | 4 ++-- src/soc/experiment/icache.py | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 82b983bd..910149e5 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -749,9 +749,9 @@ class DCache(Elaboratable, DCacheConfig): (pspec.microwatt_compat == True)) XLEN = pspec.XLEN - TLB_SET_SIZE = 16 + TLB_SET_SIZE = 8 TLB_NUM_WAYS = 2 - NUM_LINES = 16 + NUM_LINES = 8 NUM_WAYS = 2 if self.small_cache: diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index ff45332d..4e40ce40 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -344,8 +344,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig): XLEN = pspec.XLEN LINE_SIZE = 64 - TLB_SIZE = 16 - NUM_LINES = 16 + TLB_SIZE = 8 + NUM_LINES = 8 NUM_WAYS = 2 if self.small_cache: # reduce way sizes and num lines to ridiculously small -- 2.30.2