From 779656285c81f15617e621c7c4e7651e6013c7ef Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 26 Nov 2018 01:21:03 +0000 Subject: [PATCH] complete get_fetch_action, move to class Fetch --- cpu.py | 145 +++++++++++++++++++++++++-------------------------------- 1 file changed, 64 insertions(+), 81 deletions(-) diff --git a/cpu.py b/cpu.py index c73c425..f2561f1 100644 --- a/cpu.py +++ b/cpu.py @@ -177,6 +177,69 @@ class Fetch: self.output_instruction = Signal(32, name="fetch_ouutput_instruction") self.output_state = Signal(fetch_output_state,name="fetch_output_state") + def get_fetch_action(self, dc, load_store_misaligned, mi, + branch_taken, misaligned_jump_target, + csr_op_is_valid): + c = {} + c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX? + c[FOS.empty] = self.action.eq(FA.default) + c[FOS.trap] = self.action.eq(FA.ack_trap) + + # illegal instruction -> error trap + i= If((dc.act & DA.trap_illegal_instruction) != 0, + self.action.eq(FA.error_trap) + ) + + # ecall / ebreak -> noerror trap + i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0, + self.action.eq(FA.noerror_trap)) + + # load/store: check alignment, check wait + i = i.Elif((dc.act & (DA.load | DA.store)) != 0, + If((load_store_misaligned | ~mi.rw_address_valid), + self.action.eq(FA.error_trap) # misaligned or invalid addr + ).Elif(mi.rw_wait, + self.action.eq(FA.wait) # wait + ).Else( + self.action.eq(FA.default) # ok + ) + ) + + # fence + i = i.Elif((dc.act & DA.fence) != 0, + self.action.eq(FA.fence)) + + # branch -> misaligned=error, otherwise jump + i = i.Elif((dc.act & DA.branch) != 0, + If(misaligned_jump_target, + self.action.eq(FA.error_trap) + ).Else( + self.action.eq(FA.jump) + ) + ) + + # jal/jalr -> misaligned=error, otherwise jump + i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, + If(misaligned_jump_target, + self.action.eq(FA.error_trap) + ).Else( + self.action.eq(FA.jump) + ) + ) + + # csr -> opvalid=ok, else error trap + i = i.Elif((dc.act & DA.csr) != 0, + If(csr_op_is_valid, + self.action.eq(FA.default) + ).Else( + self.action.eq(FA.error_trap) + ) + ) + + c[FOS.valid] = i + + return Case(self.output_state, c) + class CPU(Module): """ @@ -214,85 +277,6 @@ class CPU(Module): for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value return Case(funct3, c) - def get_fetch_action(self, ft, dc, load_store_misaligned, mi, - branch_taken, misaligned_jump_target, - csr_op_is_valid): - c = {} - c["default"] = ft.action.eq(FA.default) # XXX hmm, should be 32'XXXXXXXX - c[FOS.empty] = ft.action.eq(FA.default) - c[FOS.trap] = ft.action.eq(FA.ack_trap) - - ifs = If((dc.act & DA.trap_illegal_instruction) != 0, - ft.action.eq(FA.error_trap) - ).Elif((dc.act & DA.trap_ecall_ebreak) != 0, - ft.action.eq(FA.noerror_trap) - ) - - c[FOS.valid] = ifs - - return Case(ft.output_state, c) - - """ - `fetch_output_state_valid: begin - if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin - get_fetch_action = `fetch_action_error_trap; - end - else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin - get_fetch_action = `fetch_action_noerror_trap; - end - else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin - if(load_store_misaligned | ~memory_interface_rw_address_valid) begin - get_fetch_action = `fetch_action_error_trap; - end - else if(memory_interface_rw_wait) begin - get_fetch_action = `fetch_action_wait; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & `decode_action_fence_i) != 0) begin - get_fetch_action = `fetch_action_fence; - end - else if((decode_action & `decode_action_branch) != 0) begin - if(branch_taken) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else - begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else if((decode_action & `decode_action_csr) != 0) begin - if(csr_op_is_valid) - get_fetch_action = `fetch_action_default; - else - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - default: - get_fetch_action = 32'hXXXXXXXX; - endcase - end - endfunction - """ - def __init__(self): self.clk = ClockSignal() self.reset = ResetSignal() @@ -533,8 +517,7 @@ class CPU(Module): csr_op_is_valid = Signal() - self.comb += self.get_fetch_action(ft, dc, - load_store_misaligned, mi, + self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi, branch_taken, misaligned_jump_target, csr_op_is_valid) if __name__ == "__main__": -- 2.30.2