From 8a428c769bbde9997551596e324b1f70a66cf6ec Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 5 May 2017 14:39:26 -0700 Subject: [PATCH] Trap superpage PTEs when PPN LSBs are set --- riscv/mmu.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv/mmu.cc b/riscv/mmu.cc index f0adb22..76a6ab1 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -197,6 +197,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_W))) { break; + } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { + break; } else { reg_t ad = PTE_A | ((type == STORE) * PTE_D); #ifdef RISCV_ENABLE_DIRTY -- 2.30.2