From cb0766a2cfa982ee8afaaea6a171ef3de71b7840 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Aug 2019 02:08:23 +0100 Subject: [PATCH 1/1] generate ilang for each part mul test --- src/ieee754/part_mul_add/test/test_multiply.py | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py index 27dfae83..409d482f 100644 --- a/src/ieee754/part_mul_add/test/test_multiply.py +++ b/src/ieee754/part_mul_add/test/test_multiply.py @@ -14,11 +14,19 @@ import unittest from hashlib import sha256 import enum import pdb +from nmigen.cli import verilog, rtlil + + +def create_ilang(dut, traces, test_name): + vl = rtlil.convert(dut, ports=traces) + with open("%s.il" % test_name, "w") as f: + f.write(vl) def create_simulator(module: Any, traces: List[Signal], test_name: str) -> Simulator: + create_ilang(module, traces, test_name) return Simulator(module, vcd_file=open(test_name + ".vcd", "w"), gtkw_file=open(test_name + ".gtkw", "w"), @@ -256,12 +264,9 @@ class TestAddReduce(unittest.TestCase): if len(register_levels) != 0: file_name += f"-{'_'.join(map(repr, register_levels))}" file_name += f"-{input_count:02d}" - with create_simulator(module, - [partition_4, - partition_8, - *inputs, - module.o.output], - file_name) as sim: + ports = [partition_4, partition_8, *inputs, module.o.output] + #create_ilang(module, ports, file_name) + with create_simulator(module, ports, file_name) as sim: self.subtest_run_sim(input_count, sim, partition_4, -- 2.30.2