From fcd0f3ab3b07b84ac2b3e62cf3534daff0fc0363 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 3 Mar 2017 18:51:37 -0800 Subject: [PATCH] sim: define emulated CPU clock rate to be 1GHz --- riscv/sim.h | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/sim.h b/riscv/sim.h index 5d165c9..f655914 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -48,6 +48,7 @@ private: void step(size_t n); // step through simulation static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core + static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; -- 2.30.2