From 02fc0fea400d9a30c2476418325cbed90e210f1c Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 8 Apr 2023 13:26:47 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls012.mdwn | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index 8d0fb34f6..2702f6297 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -17,7 +17,10 @@ months. in order to do due-diligence on the prioritisation evaluation. Otherwise the ISA WG is overwhelmed by piecemeal RFCs that may turn out not to be useful, against a background of having no guiding overview -or pre-filtering*. +or pre-filtering. Also note that the Libre-SOC Team, being funded by NLnet +under Privacy and Enhanced Trust Grants, are **prohibited** from signing +Commercial-Confidentiality NDAs, as doing so is a direct conflict of interest +with their funding body's Charitable Foundation Status and remit*. Worth bearing in mind during evaluation that every "Defined Word" may or may not be Vectoriseable, but that every "Defined Word" @@ -193,7 +196,8 @@ implement the VSX PackedSIMD paradigm, it becomes necessary to upgrade SFFS such that it is stand-alone capable. One omission based on the assumption that VSX would always be present is an equivalent to `xvtstdcsp`. -Similar arguments apply to the GPR-INT move operations, with the opportunity taken +Similar arguments apply to the GPR-INT move operations, proposed +in [[ls006]], with the opportunity taken to add rounding modes present in other ISAs that Power ISA VSX PackedSIMD does not have. Javascript rounding, one of the worst offenders of Computer Science, requires a phenomental 35 instructions with *six branches* to emulate in Power ISA! For -- 2.30.2