From 05c882e56567b5d550b697580fff4d8059c3df69 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 7 May 2019 12:36:33 +0100 Subject: [PATCH] add nmigen alu_hier to experiment --- src/experiment/alu_hier.py | 58 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 src/experiment/alu_hier.py diff --git a/src/experiment/alu_hier.py b/src/experiment/alu_hier.py new file mode 100644 index 00000000..1fc7ea0b --- /dev/null +++ b/src/experiment/alu_hier.py @@ -0,0 +1,58 @@ +from nmigen import Elaboratable, Signal, Module +from nmigen.cli import main + + +class Adder(Elaboratable): + def __init__(self, width): + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + m.d.comb += self.o.eq(self.a + self.b) + return m + + +class Subtractor(Elaboratable): + def __init__(self, width): + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + def elaborate(self, platform): + m = Module() + m.d.comb += self.o.eq(self.a - self.b) + return m + + +class ALU(Elaboratable): + def __init__(self, width): + self.op = Signal() + self.a = Signal(width) + self.b = Signal(width) + self.o = Signal(width) + + self.add = Adder(width) + self.sub = Subtractor(width) + + def elaborate(self, platform): + m = Module() + m.submodules.add = self.add + m.submodules.sub = self.sub + m.d.comb += [ + self.add.a.eq(self.a), + self.sub.a.eq(self.a), + self.add.b.eq(self.b), + self.sub.b.eq(self.b), + ] + with m.If(self.op): + m.d.comb += self.o.eq(self.sub.o) + with m.Else(): + m.d.comb += self.o.eq(self.add.o) + return m + + +if __name__ == "__main__": + alu = ALU(width=16) + main(alu, ports=[alu.op, alu.a, alu.b, alu.o]) -- 2.30.2