From 05efe9afc7dddd90f6b86829a4c0bf065f01b543 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 26 Mar 2019 02:17:52 +0000
Subject: [PATCH] add AXI4 migen

---
 shakti/m_class/AXI.mdwn | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index c2be19648..61beb10e3 100644
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -4,4 +4,8 @@ See also [[wishbone]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=10>
 * <https://github.com/alexforencich/verilog-axis>
-* https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl
+* <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
+
+# AXI4 in nmigen
+
+* <https://github.com/peteut/migen-axi>
-- 
2.30.2