From 0832d5163cfdb335b7b60b1de9c3ad1c5acd16c5 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 15 Jan 2021 19:05:36 +0100 Subject: [PATCH] add microwatt_mmu boolean variable to core and compunits --- src/soc/fu/compunits/compunits.py | 2 +- src/soc/simple/core.py | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index de88bffd..4129d368 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -238,7 +238,7 @@ class AllFunctionUnits(Elaboratable): """ - def __init__(self, pspec, pilist=None, div_fsm=True,microwatt_mmu = True): + def __init__(self, pspec, pilist=None, div_fsm=True,microwatt_mmu = False): addrwid = pspec.addr_wid units = pspec.units if not isinstance(units, dict): diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index babd3b2a..04d3604e 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -68,20 +68,16 @@ def sort_fuspecs(fuspecs): class NonProductionCore(Elaboratable): - def __init__(self, pspec): + def __init__(self, pspec, microwatt_mmu = False): self.pspec = pspec # single LD/ST funnel for memory access self.l0 = TstL0CacheBuffer(pspec, n_units=1) pi = self.l0.l0.dports[0] - if False: - # MMU / DCache - self.mmu = MMU() - self.dcache = DCache() - # function units (only one each) - self.fus = AllFunctionUnits(pspec, pilist=[pi]) + self.microwatt_mmu = microwatt_mmu + self.fus = AllFunctionUnits(pspec, pilist=[pi], microwatt_mmu = self.microwatt_mmu) # register files (yes plural) self.regs = RegFiles() -- 2.30.2