From 0df2067dae2246f52ae6f8f6578dacea1e205879 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 25 Jul 2018 07:37:17 +0100 Subject: [PATCH] add write soc function --- src/bsv/bsv_lib/soc_template.bsv | 5 +++-- src/bsv/peripheral_gen/jtag.py | 3 +++ src/bsv/pinmux_generator.py | 29 +++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index e7915c0..834e967 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -63,6 +63,7 @@ package Soc; `ifdef FlexBus import FlexBus_Types::*; `endif +{0} /*========================= */ interface Ifc_Soc; @@ -222,14 +223,14 @@ package Soc; `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif endrule rule rl_connect_interrupt_to_DMA; - Bit#(12) lv_interrupt_to_DMA= {'d-1, + Bit#(12) lv_interrupt_to_DMA= {{'d-1, `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif , `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif , `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif , 1'b1, `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif , 1'b1,1'b0, - `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }; + `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }}; dma.interrupt_from_peripherals(lv_interrupt_to_DMA); endrule `endif diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py index a409280..7f6a042 100644 --- a/src/bsv/peripheral_gen/jtag.py +++ b/src/bsv/peripheral_gen/jtag.py @@ -3,6 +3,9 @@ from bsv.peripheral_gen.base import PBase class jtag(PBase): + def slowimport(self): + return " import jtagtdm::*;\n" + def axi_slave_name(self, name, ifacenum): return '' diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 7a175ed..250d0eb 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -86,6 +86,8 @@ def pinmuxgen(pth=None, verify=True): idef = os.path.join(bp, 'instance_defines.bsv') slow = os.path.join(bp, 'slow_peripherals.bsv') slowt = os.path.join(cwd, 'slow_peripherals_template.bsv') + soc = os.path.join(bp, 'soc.bsv') + soct = os.path.join(cwd, 'soc_template.bsv') write_pmp(pmp, p, ifaces, iocells) write_ptp(ptp, p, ifaces) @@ -93,6 +95,7 @@ def pinmuxgen(pth=None, verify=True): write_bus(bus, p, ifaces) write_instances(idef, p, ifaces) write_slow(slow, slowt, p, ifaces, iocells) + write_soc(soc, soct, p, ifaces, iocells) def write_slow(slow, slowt, p, ifaces, iocells): @@ -121,6 +124,32 @@ def write_slow(slow, slowt, p, ifaces, iocells): pincon, inst, mkplic, numsloirqs, ifacedef)) +def write_soc(soc, soct, p, ifaces, iocells): + """ write out the soc.bsv file. + joins all the peripherals together as AXI Masters + """ + with open(soct) as bsv_file: + soct = bsv_file.read() + imports = ifaces.slowimport() + ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl() + regdef = ifaces.axi_reg_def() + slavedecl = ifaces.axi_slave_idx() + fnaddrmap = ifaces.axi_addr_map() + mkslow = ifaces.mkslow_peripheral() + mkcon = ifaces.mk_connection() + mkcellcon = ifaces.mk_cellconn() + pincon = ifaces.mk_pincon() + inst = ifaces.extifinstance() + mkplic = ifaces.mk_plic() + numsloirqs = ifaces.mk_sloirqsdef() + ifacedef = ifaces.mk_ext_ifacedef() + ifacedef = ifaces.mk_ext_ifacedef() + with open(soc, "w") as bsv_file: + bsv_file.write(soct.format(imports, ))#ifdecl, regdef, slavedecl, + #fnaddrmap, mkslow, mkcon, mkcellcon, + #pincon, inst, mkplic, + #numsloirqs, ifacedef)) + def write_bus(bus, p, ifaces): # package and interface declaration followed by -- 2.30.2