From 1018ea09b6d3395c9afe1e3fba869889d5e9140d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Dec 2021 07:24:11 +0000 Subject: [PATCH] wait for MMU "done" when setting PRTBL and PIDR --- src/soc/simple/test/test_core.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 341b6032..eb99ef03 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -61,6 +61,12 @@ def set_mmu_spr(name, i, val, core): # important keep pep8 formatting yield fsm.mmu.l_in.rs.eq(val) yield yield fsm.mmu.l_in.mtspr.eq(0) + while True: + done = yield fsm.mmu.l_out.done + if done: + break + yield + yield print("mmu_spr %s %d was updated %x" % (name, i, val)) @@ -153,8 +159,8 @@ def setup_regs(pdecode2, core, test): # match behaviour of SPRMap in power_decoder2.py for i, x in enumerate(SPR): if sprname == x.name: - print("setting slow SPR %d (%s) to %x" % - (i, sprname, val)) + print("setting slow SPR %d (%s/%d) to %x" % + (i, sprname, x.value, val)) if sprname in mmu_sprs: yield from set_mmu_spr(sprname, x.value, val, core) elif sprname in ldst_sprs: -- 2.30.2