From 1252412ca1f93c58e11131f591f3044b75633bb4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Sep 2021 18:59:15 +0100 Subject: [PATCH] move coresync clock synchronisation into HDLRunner --- src/soc/simple/test/test_runner.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 223d9478..130462e0 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -198,6 +198,10 @@ class HDLRunner(StateRunner): comb += self.issuer.pc_i.data.eq(self.pc_i) comb += self.issuer.svstate_i.data.eq(self.svstate_i) + # run core clock at same rate as test clock + intclk = ClockSignal("coresync") + comb += intclk.eq(ClockSignal()) + def prepare_for_test(self, test): self.test = test @@ -377,10 +381,6 @@ class TestRunner(FHDLTestCase): if self.run_sim: simrun = SimRunner(self, m, pspec) - # run core clock at same rate as test clock - intclk = ClockSignal("coresync") - comb += intclk.eq(ClockSignal()) - # nmigen Simulation - everything runs around this, so it # still has to be created. sim = Simulator(m) -- 2.30.2