From 164c1281b1d13113c31d5e77869ec84d90780644 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Wed, 1 Apr 2020 13:29:01 -0400 Subject: [PATCH] Cleanup --- src/ieee754/cordic/pipe_data.py | 4 +++- src/ieee754/cordic/sin_cos.py | 5 ++--- src/ieee754/cordic/sin_cos_pipe_stage.py | 4 ++-- src/ieee754/cordic/sin_cos_pipeline.py | 8 +++----- src/ieee754/cordic/test/test_pipe.py | 5 +---- 5 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py index a284bff1..a477d200 100644 --- a/src/ieee754/cordic/pipe_data.py +++ b/src/ieee754/cordic/pipe_data.py @@ -1,7 +1,8 @@ from nmigen import Signal, Const -from nmutil.dynamicpipe import DynamicPipe, SimpleHandshakeRedir +from nmutil.dynamicpipe import SimpleHandshakeRedir import math + class CordicInitialData: def __init__(self, pspec): @@ -14,6 +15,7 @@ class CordicInitialData: def eq(self, i): return [self.z0.eq(i.z0)] + class CordicData: def __init__(self, pspec): diff --git a/src/ieee754/cordic/sin_cos.py b/src/ieee754/cordic/sin_cos.py index cbcef5ae..fcfef762 100644 --- a/src/ieee754/cordic/sin_cos.py +++ b/src/ieee754/cordic/sin_cos.py @@ -2,7 +2,7 @@ # later be used to verify the operation of a pipelined version # see http://bugs.libre-riscv.org/show_bug.cgi?id=208 -from nmigen import Module, Elaboratable, Signal, Memory, signed +from nmigen import Module, Elaboratable, Signal, Memory from nmigen.cli import rtlil import math from enum import Enum, unique @@ -63,7 +63,6 @@ class CORDIC(Elaboratable): comb = m.d.comb sync = m.d.sync - # Calculate initial amplitude? An = 1.0 for i in range(self.iterations): @@ -118,9 +117,9 @@ class CORDIC(Elaboratable): return [self.cos, self.sin, self.z0, self.ready, self.start] + if __name__ == '__main__': dut = CORDIC(8) vl = rtlil.convert(dut, ports=dut.ports()) with open("cordic.il", "w") as f: f.write(vl) - diff --git a/src/ieee754/cordic/sin_cos_pipe_stage.py b/src/ieee754/cordic/sin_cos_pipe_stage.py index 1a1a4ec9..79ad6590 100644 --- a/src/ieee754/cordic/sin_cos_pipe_stage.py +++ b/src/ieee754/cordic/sin_cos_pipe_stage.py @@ -1,8 +1,9 @@ -from nmigen import Module, Signal, Cat, Mux +from nmigen import Module, Signal from nmutil.pipemodbase import PipeModBase from ieee754.cordic.pipe_data import CordicData, CordicInitialData import math + class CordicInitialStage(PipeModBase): def __init__(self, pspec): super().__init__(pspec, "cordicinit") @@ -28,7 +29,6 @@ class CordicInitialStage(PipeModBase): return m - class CordicStage(PipeModBase): def __init__(self, pspec, stagenum): super().__init__(pspec, "cordicstage%d" % stagenum) diff --git a/src/ieee754/cordic/sin_cos_pipeline.py b/src/ieee754/cordic/sin_cos_pipeline.py index 58d84e38..42dd6fc5 100644 --- a/src/ieee754/cordic/sin_cos_pipeline.py +++ b/src/ieee754/cordic/sin_cos_pipeline.py @@ -1,11 +1,9 @@ from nmutil.singlepipe import ControlBase -from nmutil.concurrentunit import ReservationStations, num_bits from nmutil.pipemodbase import PipeModBaseChain from ieee754.cordic.sin_cos_pipe_stage import ( CordicStage, CordicInitialStage) -from ieee754.cordic.pipe_data import (CordicPipeSpec, CordicData, - CordicInitialData) + class CordicPipeChain(PipeModBaseChain): def __init__(self, pspec, stages): @@ -14,7 +12,7 @@ class CordicPipeChain(PipeModBaseChain): def get_chain(self): return self.stages - + class CordicBasePipe(ControlBase): def __init__(self, pspec): @@ -29,7 +27,7 @@ class CordicBasePipe(ControlBase): self.cordicstages.append(stage) self._eqs = self.connect(self.cordicstages) - + def elaborate(self, platform): m = ControlBase.elaborate(self, platform) for i, stage in enumerate(self.cordicstages): diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py index bcfd563f..809ca7f7 100644 --- a/src/ieee754/cordic/test/test_pipe.py +++ b/src/ieee754/cordic/test/test_pipe.py @@ -1,5 +1,5 @@ from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Passive +from nmigen.back.pysim import Simulator, Passive from nmigen.test.utils import FHDLTestCase from ieee754.cordic.sin_cos_pipeline import CordicBasePipe @@ -57,14 +57,12 @@ class SinCosTestCase(FHDLTestCase): except StopIteration: break - sim.add_sync_process(writer_process) sim.add_sync_process(reader_process) with sim.write_vcd("pipeline.vcd", "pipeline.gtkw", traces=[ z, x, y]): sim.run() - def test_rand(self): fracbits = 16 M = (1 << fracbits) @@ -79,6 +77,5 @@ class SinCosTestCase(FHDLTestCase): self.run_test(iter(inputs), iter(outputs), fracbits=fracbits) - if __name__ == "__main__": unittest.main() -- 2.30.2