From 19b39b9e4bc07328bed90fc1e6cb3ba94ec7bac1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 7 Jun 2018 10:48:15 +0100 Subject: [PATCH] clarify --- simple_v_extension/simple_v_chennai_2018.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 43b49ff84..1b99f95cd 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -681,7 +681,7 @@ loop: (scalar ops are just vectors of length 1)\vspace{4pt} \item Tightly coupled with the core (instruction issue)\\ could be disabled through MISA switch\vspace{4pt} - \item An extra pipeline phase is pretty much essential\\ + \item An extra pipeline phase almost certainly essential\\ for fast low-latency implementations\vspace{4pt} \item With zeroing off, skipping non-predicated elements is hard:\\ it is however an optimisation (and could be skipped).\vspace{4pt} -- 2.30.2