From 1d00bee7ee08f3c746e85ebe18efbeaf1c1c8062 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 15 Jul 2018 07:38:20 +0100 Subject: [PATCH] myhdl experimentation --- src/myhdlgen/pinmux_generator.py | 42 ++++++++++-- src/myhdlgen/pins.py | 114 +++++++++++++++++++++---------- 2 files changed, 116 insertions(+), 40 deletions(-) diff --git a/src/myhdlgen/pinmux_generator.py b/src/myhdlgen/pinmux_generator.py index 47cbf45..9cf5bed 100644 --- a/src/myhdlgen/pinmux_generator.py +++ b/src/myhdlgen/pinmux_generator.py @@ -1,7 +1,7 @@ import os import sys from parse import Parse -from myhdlgen.pins import IO +from myhdlgen.pins import IO, muxgen, Mux from ifacebase import InterfacesBase try: from string import maketrans @@ -24,6 +24,19 @@ def transfn(temp): return '_'.join(temp) + +class IfPin(object): + """ pin interface declaration. + * name is the name of the pin + * ready, enabled and io all create a (* .... *) prefix + * action changes it to an "in" if true + """ + + def __init__(self, typ, name): + self.typ = typ + self.name = name + + class Interface(object): """ create an interface from a list of pinspecs. each pinspec is a dictionary, see Pin class arguments @@ -47,8 +60,8 @@ class Interface(object): for p in pinspecs: _p = {} _p['name'] = self.pname(p['name']) - _p['typ'] = self.pname(p['type']) - self.pins.append(IO(**_p)) + _p['typ'] = p['type'] + self.pins.append(IfPin(**_p)) def getifacetype(self, name): for p in self.pinspecs: @@ -81,6 +94,16 @@ class Interfaces(InterfacesBase): def __init__(self, pth=None): InterfacesBase.__init__(self, Interface, pth) +class MyHdlIface(object): + def __init__(self, iface): + self.pnames = [] + for p in iface.pins: + print "typ", p.typ, p.name + io = IO(p.typ, p.name) + setattr(self, p.name, io) + self.pnames.append(p.name) + print dir(self) + def create_module(p, ifaces): x = """\ @@ -92,16 +115,24 @@ def pinmux(muxfn, clk, p, ifaces, {0}): """ args = [] + p.muxers = [] + p.muxsel = [] for cell in p.muxed_cells: args.append("sel%d" % int(cell[0])) args.append("io%d" % int(cell[0])) + pin = IO("inout", "name%d" % int(cell[0])) + p.muxers.append(pin) + m = Mux(p.cell_bitwidth) + p.muxsel.append(m) print args - kl = sorted(ifaces.keys()) + p.myhdlifaces = [] for k, count in ifaces.ifacecount: i = ifaces[k] for c in range(count): print k args.append("%s%d" % (k, c)) + p.myhdlifaces.append(MyHdlIface(ifaces[k])) + args = ',\n\t\t'.join(args) x = x.format(args) path = os.path.abspath(__file__) @@ -136,4 +167,5 @@ def pinmuxgen(pth=None, verify=True): print (p, dir(p)) ifaces = Interfaces(pth) init(p, ifaces) - create_module(p, ifaces) + fn = create_module(p, ifaces) + muxgen(fn, p, ifaces) diff --git a/src/myhdlgen/pins.py b/src/myhdlgen/pins.py index 7a0ab3a..9ee5575 100644 --- a/src/myhdlgen/pins.py +++ b/src/myhdlgen/pins.py @@ -49,21 +49,21 @@ def Test(*args): return Foo(test2) -def create_test(npins=2, nfns=4): +def create_test(fncls, npins=2, nfns=4): x = """\ from myhdl import block @block -def test(testfn, clk, num_pins, num_fns, {0}): +def test(testfn, clk, fncls, num_pins, num_fns, {0}): args = [{0}] - return testfn(clk, num_pins, num_fns, args) + return testfn(clk, fncls, num_pins, num_fns, args) """ args = [] for pnum in range(npins): args.append("sel%d" % pnum) args.append("pin%d" % pnum) - for pnum in range(nfns): - args.append("fn%d" % pnum) + #for pnum in range(nfns): + # args.append("fn%d" % pnum) args = ','.join(args) x = x.format(args) print x @@ -86,23 +86,67 @@ def proxy(func): return func(args[0], args[1], args[2], args[3]) return wrapper +class FnCls(object): + def __init__(self): + self.attrs = ['uart', 'i2c', 'spi', 'gpio'] + + def setfn(self, idx, fn): + return setattr(self, self.attrs[idx], fn) + + def getfn(self, idx): + return getattr(self, self.attrs[idx]) @block -def test2(clk, num_pins, num_fns, args): +def muxer(clk, p, ifaces, args): muxes = [] pins = [] fns = [] + for i in range(len(p.muxed_cells)): + pins.append(args.pop(0)) + muxes.append(args.pop(0)) + kl = sorted(ifaces.keys()) + for i in range(len(p.myhdlifaces)): + fns.append(args.pop(0)) + + muxinst = [] + + inputs = [] + for i in range(2): + x = getattr(fns[i], fns[i].pnames[0]) + print x, dir(x) + inputs.append(getattr(fns[i], fns[i].pnames[0]).out) + inputs.append(getattr(fns[i], fns[i].pnames[0]).out) + + print "inputs", inputs + + for i in range(len(muxes)): + mux = muxes[i] + pin = pins[i] + print "mux", mux + print mux4 + inst = mux4(clk, inputs, mux.sel, pin.out) + muxinst.append(inst) + + return muxinst + + +@block +def test2(clk, fncls, num_pins, num_fns, args): + muxes = [] + pins = [] for i in range(num_pins): muxes.append(args.pop(0)) pins.append(args.pop(0)) - for i in range(num_fns): - fns.append(args.pop(0)) muxinst = [] inputs = [] - for i in range(4): - inputs.append(fns[i].inp) + inputs.append(fncls.uart.out) + inputs.append(fncls.i2c.out) + inputs.append(fncls.spi.out) + inputs.append(fncls.gpio.out) + #for i in range(4): + #inputs.append(fncls.getfn(i).out) for i in range(len(muxes)): mux = muxes[i] @@ -117,7 +161,7 @@ def test2(clk, num_pins, num_fns, args): @block -def mux_tb(): +def mux_tb(fncls): muxvals = [] muxes = [] @@ -125,9 +169,6 @@ def mux_tb(): ins = [] outs = [] dirs = [] - fins = [] - fouts = [] - fdirs = [] args = [] for i in range(2): m = Mux() @@ -141,16 +182,9 @@ def mux_tb(): outs.append(pin.out) dirs.append(pin.dirn) fns = [] - for i in range(4): - fn = IO("inout", "fnname%d" % i) - fns.append(fn) - fins.append(fn.inp) - fouts.append(fn.out) - fdirs.append(fn.dirn) - args.append(fn) clk = Signal(bool(0)) - mux_inst = test(test2, clk, 2, 4, *args) + mux_inst = test(test2, clk, fncls, 2, 4, *args) @instance def clk_signal(): @@ -175,7 +209,7 @@ class Deco(object): self.calls = 0 -def test_mux(): +def test_mux(fncls): muxvals = [] muxes = [] @@ -198,17 +232,9 @@ def test_mux(): ins.append(pin.inp) outs.append(pin.out) dirs.append(pin.dirn) - fns = [] - for i in range(4): - fn = IO("inout", "fnname%d" % i) - fns.append(fn) - fins.append(fn.inp) - fouts.append(fn.out) - fdirs.append(fn.dirn) - args.append(fn) clk = Signal(bool(0)) - mux_inst = test(test2, clk, 2, 4, *args) + mux_inst = test(test2, clk, fncls, 2, 4, *args) mux_inst.convert(hdl="Verilog", initial_values=True, testbench=False) #mux_inst = Test(clk, muxes, pins, fns) #toVerilog(mux_inst, clk, muxes, pins, fns) @@ -219,7 +245,7 @@ def test_mux(): #block(mux_inst).convert(hdl="Verilog", initial_values=True) # test bench - tb = mux_tb() + tb = mux_tb(fncls) tb.convert(hdl="Verilog", initial_values=True, testbench=True) # keep following lines below the 'tb.convert' line # otherwise error will be reported @@ -227,8 +253,26 @@ def test_mux(): tb.run_sim(66 * period) # run for 15 clock cycle -#test = create_test() +def muxgen(fn, p, ifaces): + args = [] + for i in range(len(p.muxed_cells)): + args.append(p.muxers[i]) + args.append(p.muxsel[i]) + for i in p.myhdlifaces: + args.append(i) + clk = Signal(bool(0)) + + mux_inst = fn(muxer, clk, p, ifaces, *args) + mux_inst.convert(hdl="Verilog", initial_values=True, testbench=False) + + if __name__ == '__main__': - test_mux() + fncls = FnCls() + num_fns = 4 + for i in range(num_fns): + fn = IO("inout", fncls.attrs[i]) + fncls.setfn(i, fn) + test = create_test(fncls) + test_mux(fncls) -- 2.30.2