From 1fa88bd555210a517c4b1a5ec213e7831349139d Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 05:55:24 +0100 Subject: [PATCH] --- Harmonised_RVV/Packed_SIMD.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn index 03d61dfa4..b863b5f98 100644 --- a/Harmonised_RVV/Packed_SIMD.mdwn +++ b/Harmonised_RVV/Packed_SIMD.mdwn @@ -37,7 +37,7 @@ However, note RV32I registers can fit 4x INT8 elements. To preserve Andes SIMD ##### Alternative register "banks" and alternative MVL -A programmer can configure VCFG with the any mix of these alternative configurations: +A programmer can configure VCFG with any mix of these alternative configurations: * v0-v31 are all INT 16, and MVL is same as for Default MVL above * v0-v31 are all INT 8 and MVL is 4 on RV32I and 8 on RV64I -- 2.30.2