From 20ff27ba59ad9175082d72342b49871b913cb1d5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 13 Nov 2021 18:06:12 +0000 Subject: [PATCH] tidyup, got testing_stage1.py at least running --- src/spec/testing_stage1.py | 73 ++++++++++++++++++++++++++++---------- 1 file changed, 54 insertions(+), 19 deletions(-) diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index 00af2ac..c148598 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -1,11 +1,17 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 from nmigen.build.dsl import Resource, Subsignal, Pins -from nmigen.build.plat import Platform # Not sure where platform comes from? +from nmigen.build.plat import TemplatedPlatform +from nmigen import Elaboratable, Signal, Module # Was thinking of using these functions, but skipped for simplicity for now -#from pinfunctions import i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi, quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1, flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio +# XXX nope. the output from JSON file. +#from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi, +# quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1, +# flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio) + +# File for stage 1 pinmux tested proposed by Luke, +https://bugs.libre-soc.org/show_bug.cgi?id=50#c10 -# File for stage 1 pinmux tested proposed by Luke, https://bugs.libre-soc.org/show_bug.cgi?id=50#c10 def dummy_pinset(): # sigh this needs to come from pinmux. @@ -27,39 +33,68 @@ into: ... ] """ + + def create_resources(pinset): resources = [] for periph, pins in pinset.items(): print(periph, pins) if periph == 'i2c': #print("I2C required!") - resources.append(I2CResource('i2c', 0, sda='sda0', scl='scl0')) + resources.append(I2CResource('i2c', 0, sda='sda', scl='scl')) elif periph == 'uart': #print("UART required!") - resources.append(UARTResource('uart', 0, tx='tx0', rx='rx0')) + resources.append(UARTResource('uart', 0, tx='tx', rx='rx')) elif periph == 'gpio': #print("GPIO required!") - resources.append(Resource('gpio', 0, Subsignal("i", Pins('i0', dir="i", conn=None, assert_width=1)), Subsignal("o", Pins('o0', dir="o", conn=None, assert_width=1)))) + print ("GPIO is defined as '*' type, meaning i, o and oe needed") + resources.append(Resource('gpio', 0, + Subsignal("i", Pins('i0', dir="i", conn=None, assert_width=1)), + Subsignal("oe", Pins('oe0', dir="o", conn=None, assert_width=1)), + Subsignal("o", Pins('o0', dir="o", conn=None, assert_width=1)))) return resources -def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None, - conn=None, attrs=None, role=None): + +def UARTResource(*args, rx, tx): io = [] - io.append(Subsignal("rx", Pins(rx, dir="i", conn=conn, assert_width=1))) - io.append(Subsignal("tx", Pins(tx, dir="o", conn=conn, assert_width=1))) - if attrs is not None: - io.append(attrs) + io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1))) + io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1))) return Resource.family(*args, default_name="uart", ios=io) -def I2CResource(*args, scl, sda, conn=None, attrs=None): + +def I2CResource(*args, scl, sda): io = [] - io.append(Subsignal("scl", Pins(scl, dir="io", conn=conn, assert_width=1))) - io.append(Subsignal("sda", Pins(sda, dir="io", conn=conn, assert_width=1))) - if attrs is not None: - io.append(attrs) + io.append(Subsignal("scl", Pins(scl, dir="io", assert_width=1))) + io.append(Subsignal("sda", Pins(sda, dir="io", assert_width=1))) return Resource.family(*args, default_name="i2c", ios=io) +# ridiculously-simple top-level module. doesn't even have a sync domain +# and can't have one until a clock has been established by DummyPlatform. +class Blinker(Elaboratable): + def __init__(self): + pass + def elaborate(self, platform): + m = Module() + count = Signal(5) + m.d.comb += count.eq(5) + return m + + +# sigh, have to create a dummy platform for now. +# TODO: investigate how the heck to get it to output ilang. or verilog. +# or, anything, really. but at least it doesn't barf +class DummyPlatform(TemplatedPlatform): + resources = [] + connectors = [] + required_tools = [] + command_templates = ['/bin/true'] + file_templates = TemplatedPlatform.build_script_templates + toolchain = None + def __init__(self, resources): + self.resources = resources + super().__init__() + """ and to create a Platform instance with that list, and build something random @@ -72,7 +107,7 @@ pinset = dummy_pinset() resources = create_resources(pinset) print(pinset) print(resources) -p=Platform(resources) +p = DummyPlatform (resources) p.resources = create_resources(pinset) p.build(Blinker()) -- 2.30.2