From 21a7dc2c0f2037f5a9ebd4ce16bb6ba0bdbbfc41 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 28 May 2019 05:10:10 +0100 Subject: [PATCH] reword multiplier section --- updates/018_2019may27_nlnet_grant_approved.mdwn | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/updates/018_2019may27_nlnet_grant_approved.mdwn b/updates/018_2019may27_nlnet_grant_approved.mdwn index a877257..f6451f6 100644 --- a/updates/018_2019may27_nlnet_grant_approved.mdwn +++ b/updates/018_2019may27_nlnet_grant_approved.mdwn @@ -75,12 +75,12 @@ Adder and Multiplier Unit. Given that we are doing a Vector Processing front-end onto SIMD back-end operations, it makes sense to save gates by allowing the ADD and MUL units to be able to optionally handle a batch of 8-bit operations, or half the number of 16-bit operations, or a quarter -of the number of 32-bit operations or just one 64-bit operation. +of the number of 32-bit operations or just one 64-bit operation. Or, +it can be used to do two 64-bit multiplications per cycle, or generate +4 32-bit results, or 8 16-bit results and so on, requiring a lot less gates +than if they were separate units. The unit tests demonstrate that the code that Jacob has written provide -RISC-V mul, mulh, mulhu and mulhsu functionality. The pipelined version -should be particularly interesting, for doing 64-bit multiply, although -64 performance is not a high priority in this design, so could be done -as an FSM. +RISC-V mul, mulh, mulhu and mulhsu functionality. The augmented 6600 Scoreboard took literally six weeks to correctly implement Read-after-Write and Write-after-Read hazards. It required extraordinary -- 2.30.2