From 23505ed4eb98ba9c3bcc500ced0f495cef1613a4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 14 Sep 2020 13:24:23 +0100 Subject: [PATCH] fix mmu perms/lookup in dcache --- src/soc/experiment/dcache.py | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index b23c46e3..114aa0d2 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -264,12 +264,6 @@ class PermAttr(RecordObject): def extract_perm_attr(pte): pa = PermAttr() - pa.reference = pte[8] - pa.changed = pte[7] - pa.nocache = pte[5] - pa.priv = pte[3] - pa.rd_perm = pte[2] - pa.wr_perm = pte[1] return pa; @@ -601,7 +595,7 @@ class DCache(Elaboratable): sync += r.req.dcbz.eq(0) sync += r.req.nc.eq(0) sync += r.req.reserve.eq(0) - sync += r.req.virt_mode.eq(1) + sync += r.req.virt_mode.eq(0) sync += r.req.priv_mode.eq(1) sync += r.req.addr.eq(m_in.addr) sync += r.req.data.eq(m_in.pte) @@ -687,7 +681,7 @@ class DCache(Elaboratable): for i in range(TLB_NUM_WAYS): is_tag_hit = Signal() comb += is_tag_hit.eq(tlb_valid_way[i] - & read_tlb_tag(i, tlb_tag_way) == eatag) + & (read_tlb_tag(i, tlb_tag_way) == eatag)) with m.If(is_tag_hit): comb += hitway.eq(i) comb += hit.eq(1) @@ -704,7 +698,12 @@ class DCache(Elaboratable): comb += ra.eq(Cat(Const(0, ROW_OFF_BITS), r0.req.addr[ROW_OFF_BITS:TLB_LG_PGSZ], pte[TLB_LG_PGSZ:REAL_ADDR_BITS])) - comb += perm_attr.eq(extract_perm_attr(pte)) + comb += perm_attr.reference.eq(pte[8]) + comb += perm_attr.changed.eq(pte[7]) + comb += perm_attr.nocache.eq(pte[5]) + comb += perm_attr.priv.eq(pte[3]) + comb += perm_attr.rd_perm.eq(pte[2]) + comb += perm_attr.wr_perm.eq(pte[1]) with m.Else(): comb += ra.eq(Cat(Const(0, ROW_OFF_BITS), r0.req.addr[ROW_OFF_BITS:REAL_ADDR_BITS])) -- 2.30.2