From 256cddfd1c2dd16b652a94130830a8c9cd80e0ac Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 31 Jan 2022 15:06:56 +0000 Subject: [PATCH] use Memory for cache tags in dcache --- src/soc/experiment/dcache.py | 44 ++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 282a2955..4dc11e8a 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -83,9 +83,9 @@ from nmutil.util import wrap # TODO: make these parameters of DCache at some point LINE_SIZE = 64 # Line size in bytes NUM_LINES = 64 # Number of lines in a set -NUM_WAYS = 2 # Number of ways +NUM_WAYS = 1 # Number of ways TLB_SET_SIZE = 64 # L1 DTLB entries per set -TLB_NUM_WAYS = 2 # L1 DTLB number of sets +TLB_NUM_WAYS = 1 # L1 DTLB number of sets TLB_LG_PGSZ = 12 # L1 DTLB log_2(page_size) LOG_LENGTH = 0 # Non-zero to enable log data collection @@ -931,14 +931,17 @@ class DCache(Elaboratable): comb += plrus.isel.eq(r1.store_index) # select victim comb += plru_victim.eq(plrus.o_index) # selected victim - def cache_tag_read(self, m, r0_stall, req_index, cache_tag_set, - cache_tags): + def cache_tag_read(self, m, r0_stall, req_index, cache_tag_set): """Cache tag RAM read port """ comb = m.d.comb sync = m.d.sync + m_in, d_in = self.m_in, self.d_in + # synchronous tag read-port + m.submodules.rd_tag = rd_tag = self.tagmem.read_port() + index = Signal(INDEX_BITS) with m.If(r0_stall): @@ -947,10 +950,11 @@ class DCache(Elaboratable): comb += index.eq(get_index(m_in.addr)) with m.Else(): comb += index.eq(get_index(d_in.addr)) - sync += cache_tag_set.eq(cache_tags[index]) + comb += rd_tag.addr.eq(index) + comb += cache_tag_set.eq(rd_tag.data) # read-port is a 1-clock delay def dcache_request(self, m, r0, ra, req_index, req_row, req_tag, - r0_valid, r1, cache_tags, cache_valids, replace_way, + r0_valid, r1, cache_valids, replace_way, use_forward1_next, use_forward2_next, req_hit_way, plru_victim, rc_ok, perm_attr, valid_ra, perm_ok, access_ok, req_op, req_go, @@ -1345,13 +1349,16 @@ class DCache(Elaboratable): def dcache_slow(self, m, r1, use_forward1_next, use_forward2_next, r0, replace_way, req_hit_way, req_same_tag, - r0_valid, req_op, cache_tags, cache_valids, req_go, ra): + r0_valid, req_op, cache_valids, req_go, ra): comb = m.d.comb sync = m.d.sync bus = self.bus d_in = self.d_in + m.submodules.wr_tag = wr_tag = self.tagmem.write_port( + granularity=TAG_WIDTH) + req = MemAccessRequest("mreq_ds") r1_next_cycle = Signal() @@ -1407,12 +1414,12 @@ class DCache(Elaboratable): # Store new tag in selected way replace_way_onehot = Signal(NUM_WAYS) comb += replace_way_onehot.eq(1<