From 25a35f2c7e3177f375db3302c68111877a046c49 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 16 Apr 2023 14:06:36 +0100 Subject: [PATCH] --- openpower/sv/remap.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index fe2055661..6bbfb88a6 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -334,7 +334,9 @@ with an Index exceeding VL-1.* Vector Reduce Mode issues a deterministic tree-reduction schedule to the underlying micro-architecture. Like Scalar reduction, the "Scalar Base" (Power ISA v3.0B) operation is leveraged, unmodified, to give the -*appearance* and *effect* of Reduction. +*appearance* and *effect* of Reduction. Parallel Reduction is not limited +to Power-of-two but is limited as usual by the total number of +element operations (127) as well as available register file size. In Horizontal-First Mode, Vector-result reduction **requires** the destination to be a Vector, which will be used to store -- 2.30.2