From 2674696760ff3d1b8981120f9a7eaa258550ae96 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Dec 2021 02:44:57 +0000 Subject: [PATCH] whoops, use MSR.IR for I-Cache fetch! virtual memory instruction fetch uses MSR.IR not MSR.DR --- src/soc/simple/issuer.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index ffb7dc97..ab414f52 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -713,7 +713,7 @@ class FetchFSM(ControlBase): # set priv / virt mode on I-Cache, sigh if isinstance(self.imem, ICache): comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR]) - comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR]) + comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM) with m.FSM(name='fetch_fsm'): -- 2.30.2