From 26ee3f2ec143ea093b2353b68d9b8e383fd11dc5 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 28 Jun 2022 10:36:53 +0100
Subject: [PATCH]

---
 openpower/sv/branches.mdwn | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index fb9b9da34..5f5be19fb 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -168,8 +168,6 @@ Conditional:
 |ALL|SNZ|CTi| / | SL |SLu | 1  | 0  | /   | LRu sz | CTR-test mode         |
 |ALL|SNZ|CTi|VSb| SL |SLu | 1  | 1  | VLI | LRu sz | CTR-test+VLSET mode   |
 
-TODO bits 17,18 for SVSTATE-variant of LR and LRu.
-
 Brief description of fields:
 
 * **sz=1** if predication is enabled and `sz=1` and a predicate
@@ -195,6 +193,10 @@ Brief description of fields:
   If VLI (Vector Length Inclusive) is clear,
   VL is truncated to *exclude* the current element, otherwise it is
   included. SVSTATE.MVL is not altered: only VL.
+* **SL** identical to `LR` except applicable to SVSTATE. If `SL`
+  is set, SVSTATE is transferred to SVLR (conditionally on
+  whether `SLu` is set).
+* **SLu**: SVSTATE Link Update, like `LRu` except applies to SVSTATE.
 * **LRu**: Link Register Update, used in conjunction with LK=1
   to make LR update conditional
 * **VSb** In VLSET Mode, after testing,
-- 
2.30.2