From 2c6f570819d17cd3bfab9a9f807683c631b3429d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 Jan 2022 01:42:07 +0000 Subject: [PATCH] missed setting r1.store_way and r1.store_row in STORE_WAIT_ACK state --- src/soc/experiment/dcache.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 374297ba..612e6c21 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1606,10 +1606,12 @@ class DCache(Elaboratable): sync += r1.wb.sel.eq(req.byte_sel) with m.If((adjust_acks < 7) & req.same_tag & - ((req.op == Op.OP_STORE_MISS) - | (req.op == Op.OP_STORE_HIT))): + ((req.op == Op.OP_STORE_MISS) | + (req.op == Op.OP_STORE_HIT))): sync += r1.wb.stb.eq(1) comb += st_stbs_done.eq(0) + sync += r1.store_way.eq(req.hit_way) + sync += r1.store_row.eq(get_row(req.real_addr)) with m.If(req.op == Op.OP_STORE_HIT): sync += r1.write_bram.eq(1) -- 2.30.2