From 2ee653d030e00ffd1e1a93644088e6f2fee59650 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Tue, 1 Nov 2022 14:49:09 +0000 Subject: [PATCH] ls004: Adjusted word desc based on Lukes c#8, bug #968 --- openpower/sv/rfc/ls004.mdwn | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/openpower/sv/rfc/ls004.mdwn b/openpower/sv/rfc/ls004.mdwn index 347f27ceb..a8afce0c3 100644 --- a/openpower/sv/rfc/ls004.mdwn +++ b/openpower/sv/rfc/ls004.mdwn @@ -96,9 +96,10 @@ Pseudocode: sum[0:63] <- ((RB) << shift) + (RA) # Shift RB, add RA RT <- sum # Result stored in RT -`shift` is determined by the 2-bit bitfield `sm`+1. -The minimum shift as 1, maximum 4. -The result is shifted (RB) + (RA), and is stored in register RT. +When `sm` is zero, the contents of register RB are multiplied by 2, +added to the contents of register RA, and the result stored in RT. + +`sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16. Operands RA and RB, and the result RT are all 64-bit, unsigned integers. @@ -120,15 +121,15 @@ shadd r4, r1, r2, 3 Pseudocode: - shift <- shift + 1 # Shift is between 1-4 + shift <- sm + 1 # Shift is between 1-4 n <- (RB)[XLEN/2:XLEN-1] # Limit RB to upper word (32-bits) sum[0:63] <- (n << shift) + (RA) # Shift n, add RA RT <- sum # Result stored in RT -`shift` is determined by the 2-bit bitfield `sm`+1. -Mask (RB) to only use the upper word (32-bits). -The minimum shift as 1, maximum 4. -The result is shifted `n` + (RA), and is stored in register RT. +When `sm` is zero, the upper word contents of register RB are multiplied by 2, +added to the contents of register RA, and the result stored in RT. + +`sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16. Operands RA and RB, and the result RT are all 64-bit, unsigned integers. -- 2.30.2