From 314c4130602c897d99b7ca9b3af1332df1070bee Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 10:43:52 +0100 Subject: [PATCH] whoops set pass_flag[0] always true rather than pass_flag[-1] always false --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index d6727dc0..b9a4ee56 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -413,16 +413,15 @@ class DivPipeCoreCalculateStage(Elaboratable): comb += t.compare_rhs.eq(self.i.compare_rhs) comb += t.operation.eq(self.i.operation) - # get the trial output + # get the trial output (needed even in pass_flags[0] case) trial_compare_rhs_values.append(t.trial_compare_rhs) # make the trial comparison against the [invariant] lhs. # trial_compare_rhs is always decreasing as trial_bits increases pass_flag = Signal(name=f"pass_flag_{trial_bits}", reset_less=True) - if trial_bits == radix-1: - # do not do last comparison: no point. if all others - # fail we pick this one anyway. - comb += pass_flag.eq(0) + if trial_bits == 0: + # do not do first comparison: no point. + comb += pass_flag.eq(1) else: comb += pass_flag.eq(self.i.compare_lhs >= t.trial_compare_rhs) pfl.append(pass_flag) -- 2.30.2