From 3188f922c069f7958a1808652f3368a51d31a85a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 17 Jan 2022 18:00:52 +0000 Subject: [PATCH] fix hrfid and mtmsrd so that it is identical to microwatt both allow MSR.ME to be set, which walks linux-5.7 along a different codepath particularly for 0x900 exception handling --- src/soc/fu/trap/main_stage.py | 24 ++++++++++++++++-------- src/soc/simple/test/test_issuer.py | 2 ++ src/soc/simple/test/test_runner.py | 4 ++++ 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 116be81a..1685f3f2 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -267,9 +267,13 @@ class TrapMainStage(PipeModBase): # hypervisor stuff. here: bits 3 (HV) and 51 (ME) were # copied over by msr_copy but if HV was not set we need # the *original* (msr_i) bits - with m.If(~msr_i[MSR.HV]): - comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV]) - comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME]) + # XXX taking this out to see what happens when running + # linux-5.7 microwatt buildroot. microwatt does not + # implement HV, so this is unlikely to work. 0x900 + # linux kernel exception handling tends to support this + # with m.If(~msr_i[MSR.HV]): + # comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV]) + # comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME]) comb += msr_o.ok.eq(1) @@ -297,11 +301,15 @@ class TrapMainStage(PipeModBase): # MSR was in srr1: copy it over, however *caveats below* comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero - with m.If(~self.i.ctx.op.insn[9]): # XXX BAD HACK! (hrfid) - with m.If(field(msr_i, 3)): # HV - comb += field(msr_o, 51).eq(field(srr1_i, 51)) # ME - with m.Else(): - comb += field(msr_o, 51).eq(field(msr_i, 51)) # ME + if False: # XXX no - not doing hypervisor yet + with m.If(~self.i.ctx.op.insn[9]): # XXX BAD HACK! (hrfid) + with m.If(field(msr_i, 3)): # HV + comb += field(msr_o, 51).eq(field(srr1_i, 51)) # ME + with m.Else(): + comb += field(msr_o, 51).eq(field(msr_i, 51)) # ME + else: + # same as microwatt: treat MSR.ME rfid same as hrfid + comb += field(msr_o, 51).eq(field(srr1_i, 51)) # ME # check problem state: if set, not permitted to set EE,IR,DR msr_check_pr(m, srr1_i, msr_o.data) diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index b5799ecf..b86e162e 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -30,6 +30,7 @@ from openpower.test.cr.cr_cases import CRTestCase from openpower.test.branch.branch_cases import BranchTestCase from soc.fu.spr.test.test_pipe_caller import SPRTestCase from openpower.test.ldst.ldst_cases import LDSTTestCase +from openpower.test.trap.trap_cases import TrapTestCase from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase) from openpower.simulator.test_helloworld_sim import HelloTestCases @@ -83,6 +84,7 @@ if __name__ == "__main__": 'hazard': HazardTestCase().test_data, 'alu': ALUTestCase().test_data, 'branch': BranchTestCase().test_data, + 'trap': TrapTestCase().test_data, 'spr': SPRTestCase().test_data } diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index b4458c0c..5d6e57da 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -373,6 +373,10 @@ class HDLRunner(StateRunner): xer = yield from get_dmi(self.dmi, DBGCore.XER) print("after test %s XER value %x" % (self.test.name, xer)) + # get MSR + msr = yield from get_dmi(self.dmi, DBGCore.MSR) + print("after test %s MSR value %x" % (self.test.name, msr)) + # test of dmi reg get for int_reg in range(32): yield from set_dmi(self.dmi, DBGCore.GSPR_IDX, int_reg) -- 2.30.2