From 3309a6a452b6ccc5f90eb1c7771a098fc8343763 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Dec 2022 13:04:51 +0000 Subject: [PATCH] mention SVP64 in ls005 --- openpower/sv/rfc/ls005.mdwn | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn index a66b4234e..22888b94c 100644 --- a/openpower/sv/rfc/ls005.mdwn +++ b/openpower/sv/rfc/ls005.mdwn @@ -85,6 +85,11 @@ this with the more "normal" approach of creating heavily-focussed specialist "AI" Engines incapable of Turing-completeness and the benefits are clear. +Note: SVP64 **requires** this change as a 100% critical dependency. +SIMD back-end ALUs process Vectors of "Elements" at 8, 16 and 32-bit (and +64-bit), read from, processed, and returned to, the standard **Scalar** +Register Files, with byte-level write-enable lines. + **Changes** For all pseudocode right across the board in all Scalar operations, replace -- 2.30.2