From 358de3c5a0471aaf426d77da9f4a809c8edb0f55 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Tue, 28 Jun 2022 15:07:45 +0100 Subject: [PATCH] Added ls2 pinout --- crypto_router_asic/ls2.mdwn | 615 ++++++++++++++++++++++++++++++++++++ 1 file changed, 615 insertions(+) create mode 100644 crypto_router_asic/ls2.mdwn diff --git a/crypto_router_asic/ls2.mdwn b/crypto_router_asic/ls2.mdwn new file mode 100644 index 000000000..506a3bf04 --- /dev/null +++ b/crypto_router_asic/ls2.mdwn @@ -0,0 +1,615 @@ +# Pinouts (PinMux) +auto-generated by [[pinouts.py]] + +[[!toc ]] + + +## Bank N (32 pins, width 4) + +| Pin | Mux0 | Mux1 | Mux2 | Mux3 | +| --- | ----------- | ----------- | ----------- | ----------- | +| 0 | N GPION_N0 | N RG0_ERXD0 | | | +| 1 | N GPION_N1 | N RG0_ERXD1 | | | +| 2 | N GPION_N2 | N RG0_ERXD2 | | | +| 3 | N GPION_N3 | N RG0_ERXD3 | | | +| 4 | N VSSE_6 | | | | +| 5 | N VDDE_6 | | | | +| 6 | N VDDI_6 | | | | +| 7 | N VSSI_6 | | | | +| 8 | N GPION_N4 | N RG0_ETXD0 | | | +| 9 | N GPION_N5 | N RG0_ETXD1 | | | +| 10 | N GPION_N6 | N RG0_ETXD2 | | | +| 11 | N GPION_N7 | N RG0_ETXD3 | | | +| 12 | N GPION_N8 | N RG0_ERXCK | | | +| 13 | N GPION_N9 | N RG0_ERXERR | | | +| 14 | N GPION_N10 | N RG0_ERXDV | | | +| 15 | N GPION_N11 | N RG0_EMDC | | | +| 16 | N GPION_N12 | N RG0_EMDIO | | | +| 17 | N GPION_N13 | N RG0_ETXEN | | | +| 18 | N GPION_N14 | N RG0_ETXCK | | | +| 19 | N GPION_N15 | N RG0_ECRS | | | +| 20 | N GPION_N16 | N RG0_ECOL | | | +| 21 | N GPION_N17 | N RG0_ETXERR | | | +| 23 | N VSSI_7 | | | | +| 24 | N VDDI_7 | | | | +| 25 | N VSSE_7 | | | | +| 26 | N VDDE_7 | | | | +| 27 | N SYS_RST | | | | +| 28 | N SYS_PLLCLK | | | | +| 29 | N SYS_PLLSELA0 | | | | +| 30 | N SYS_PLLSELA1 | | | | +| 31 | N SYS_PLLTESTOUT | | | | + +## Bank E (32 pins, width 4) + +| Pin | Mux0 | Mux1 | Mux2 | Mux3 | +| --- | ----------- | ----------- | ----------- | ----------- | +| 32 | E GPIOE_E0 | E RG1_ERXD0 | | | +| 33 | E GPIOE_E1 | E RG1_ERXD1 | | | +| 34 | E GPIOE_E2 | E RG1_ERXD2 | | | +| 35 | E GPIOE_E3 | E RG1_ERXD3 | | | +| 36 | E VSSE_4 | | | | +| 37 | E VDDE_4 | | | | +| 38 | E VDDI_4 | | | | +| 39 | E VSSI_4 | | | | +| 40 | E GPIOE_E6 | E RG1_ETXD0 | | | +| 41 | E GPIOE_E7 | E RG1_ETXD1 | | | +| 42 | E GPIOE_E8 | E RG1_ETXD2 | | | +| 43 | E GPIOE_E9 | E RG1_ETXD3 | | | +| 44 | E GPIOE_E10 | E RG1_ERXCK | | | +| 45 | E GPIOE_E11 | E RG1_ERXERR | | | +| 46 | E GPIOE_E12 | E RG1_ERXDV | | | +| 47 | E GPIOE_E13 | E RG1_EMDC | | | +| 48 | E GPIOE_E14 | E RG1_EMDIO | | | +| 49 | E GPIOE_E15 | E RG1_ETXEN | | | +| 50 | E JTAG_TMS | | | | +| 51 | E JTAG_TDI | | | | +| 52 | E JTAG_TDO | | | | +| 53 | E JTAG_TCK | | | | +| 54 | E VSSI_5 | | | | +| 55 | E VDDI_5 | | | | +| 56 | E VSSE_5 | | | | +| 57 | E VDDE_5 | | | | +| 58 | E GPIOE_E16 | E RG1_ETXCK | | | +| 59 | E GPIOE_E17 | E RG1_ECRS | | | +| 60 | E GPIOE_E18 | E RG1_ECOL | E EINT_0 | | +| 61 | E GPIOE_E19 | E RG1_ETXERR | E EINT_1 | | +| 62 | E GPIOE_E20 | | E EINT_2 | | +| 63 | E SYS_PLLVCOUT | | | | + +## Bank S (32 pins, width 4) + +| Pin | Mux0 | Mux1 | Mux2 | Mux3 | +| --- | ----------- | ----------- | ----------- | ----------- | +| 64 | S GPIOS_S0 | S SDR_AD10 | | | +| 65 | S GPIOS_S1 | S SDR_AD11 | | | +| 66 | S GPIOS_S2 | S SDR_AD12 | | | +| 67 | S GPIOS_S3 | S SDR_DQM1 | | | +| 68 | S VDDE_2 | | | | +| 69 | S VSSE_2 | | | | +| 70 | S VDDI_2 | | | | +| 71 | S VSSI_2 | | | | +| 72 | S GPIOS_S4 | S SDR_D8 | | | +| 73 | S GPIOS_S5 | S SDR_D9 | | | +| 74 | S GPIOS_S6 | S SDR_D10 | | | +| 75 | S GPIOS_S7 | S SDR_D11 | | | +| 76 | S GPIOS_S8 | S SDR_D12 | | | +| 77 | S GPIOS_S9 | S SDR_D13 | | | +| 78 | S GPIOS_S10 | S SDR_D14 | | | +| 79 | S GPIOS_S11 | S SDR_D15 | | | +| 80 | S GPIOS_S12 | S SDR_CLK | | | +| 81 | S GPIOS_S13 | S SDR_CKE | | | +| 82 | S GPIOS_S14 | S SDR_RASn | | | +| 83 | S GPIOS_S15 | S SDR_CASn | | | +| 84 | S GPIOS_S16 | S SDR_WEn | | | +| 85 | S GPIOS_S17 | S SDR_CSn0 | | | +| 86 | S VSSI_3 | | | | +| 87 | S VDDI_3 | | | | +| 88 | S VSSE_3 | | | | +| 89 | S VDDE_3 | | | | +| 90 | S GPIOS_S18 | S UART0_TX | | | +| 91 | S GPIOS_S19 | S UART0_RX | | | +| 92 | S GPIOS_S20 | S MSPI0_CK | | | +| 93 | S GPIOS_S21 | S MSPI0_NSS | | | +| 94 | S GPIOS_S22 | S MSPI0_MOSI | | | +| 95 | S GPIOS_S23 | S MSPI0_MISO | | | + +## Bank W (32 pins, width 4) + +| Pin | Mux0 | Mux1 | Mux2 | Mux3 | +| --- | ----------- | ----------- | ----------- | ----------- | +| 96 | W GPIOW_W0 | W SDR_AD9 | | | +| 97 | W GPIOW_W1 | W SDR_AD8 | | | +| 98 | W GPIOW_W2 | W SDR_AD7 | | | +| 99 | W GPIOW_W3 | W SDR_AD6 | | | +| 100 | W GPIOW_W4 | W SDR_AD5 | | | +| 101 | W GPIOW_W5 | W SDR_AD4 | | | +| 102 | W VDDE_0 | | | | +| 103 | W VSSE_0 | | | | +| 104 | W VDDI_0 | | | | +| 105 | W VSSI_0 | | | | +| 106 | W GPIOW_W6 | W SDR_AD3 | | | +| 107 | W GPIOW_W7 | W SDR_AD2 | | | +| 108 | W GPIOW_W8 | W SDR_AD1 | | | +| 109 | W GPIOW_W9 | W SDR_AD0 | | | +| 110 | W GPIOW_W10 | W SDR_BA1 | | | +| 111 | W GPIOW_W11 | W SDR_BA0 | | | +| 112 | W GPIOW_W12 | W SDR_D7 | | | +| 113 | W GPIOW_W13 | W SDR_D6 | | | +| 114 | W GPIOW_W14 | W SDR_D5 | | | +| 115 | W GPIOW_W15 | W SDR_D4 | | | +| 116 | W GPIOW_W16 | W SDR_D3 | | | +| 117 | W GPIOW_W17 | W SDR_D2 | | | +| 118 | W GPIOW_W18 | W SDR_D1 | | | +| 119 | W GPIOW_W19 | W SDR_D0 | | | +| 120 | W GPIOW_W20 | W SDR_DQM0 | | | +| 121 | W VSSI_1 | | | | +| 122 | W VDDI_1 | | | | +| 123 | W VSSE_1 | | | | +| 124 | W VDDE_1 | | | | +| 125 | W GPIOW_W21 | | | | +| 126 | W GPIOW_W22 | W MTWI_SDA | | | +| 127 | W GPIOW_W23 | W MTWI_SCL | | | + +# Pinouts (Fixed function) + +# Functions (PinMux) + +auto-generated by [[pinouts.py]] + +## EINT + +External Interrupt + +* EINT_0 : E28/2 +* EINT_1 : E29/2 +* EINT_2 : E30/2 + +## GPIO + +GPIO + +* GPIOE_E0 : E0/0 +* GPIOE_E1 : E1/0 +* GPIOE_E10 : E12/0 +* GPIOE_E11 : E13/0 +* GPIOE_E12 : E14/0 +* GPIOE_E13 : E15/0 +* GPIOE_E14 : E16/0 +* GPIOE_E15 : E17/0 +* GPIOE_E16 : E26/0 +* GPIOE_E17 : E27/0 +* GPIOE_E18 : E28/0 +* GPIOE_E19 : E29/0 +* GPIOE_E2 : E2/0 +* GPIOE_E20 : E30/0 +* GPIOE_E3 : E3/0 +* GPIOE_E6 : E8/0 +* GPIOE_E7 : E9/0 +* GPIOE_E8 : E10/0 +* GPIOE_E9 : E11/0 +* GPION_N0 : N0/0 +* GPION_N1 : N1/0 +* GPION_N10 : N14/0 +* GPION_N11 : N15/0 +* GPION_N12 : N16/0 +* GPION_N13 : N17/0 +* GPION_N14 : N18/0 +* GPION_N15 : N19/0 +* GPION_N16 : N20/0 +* GPION_N17 : N21/0 +* GPION_N2 : N2/0 +* GPION_N3 : N3/0 +* GPION_N4 : N8/0 +* GPION_N5 : N9/0 +* GPION_N6 : N10/0 +* GPION_N7 : N11/0 +* GPION_N8 : N12/0 +* GPION_N9 : N13/0 +* GPIOS_S0 : S0/0 +* GPIOS_S1 : S1/0 +* GPIOS_S10 : S14/0 +* GPIOS_S11 : S15/0 +* GPIOS_S12 : S16/0 +* GPIOS_S13 : S17/0 +* GPIOS_S14 : S18/0 +* GPIOS_S15 : S19/0 +* GPIOS_S16 : S20/0 +* GPIOS_S17 : S21/0 +* GPIOS_S18 : S26/0 +* GPIOS_S19 : S27/0 +* GPIOS_S2 : S2/0 +* GPIOS_S20 : S28/0 +* GPIOS_S21 : S29/0 +* GPIOS_S22 : S30/0 +* GPIOS_S23 : S31/0 +* GPIOS_S3 : S3/0 +* GPIOS_S4 : S8/0 +* GPIOS_S5 : S9/0 +* GPIOS_S6 : S10/0 +* GPIOS_S7 : S11/0 +* GPIOS_S8 : S12/0 +* GPIOS_S9 : S13/0 +* GPIOW_W0 : W0/0 +* GPIOW_W1 : W1/0 +* GPIOW_W10 : W14/0 +* GPIOW_W11 : W15/0 +* GPIOW_W12 : W16/0 +* GPIOW_W13 : W17/0 +* GPIOW_W14 : W18/0 +* GPIOW_W15 : W19/0 +* GPIOW_W16 : W20/0 +* GPIOW_W17 : W21/0 +* GPIOW_W18 : W22/0 +* GPIOW_W19 : W23/0 +* GPIOW_W2 : W2/0 +* GPIOW_W20 : W24/0 +* GPIOW_W21 : W29/0 +* GPIOW_W22 : W30/0 +* GPIOW_W23 : W31/0 +* GPIOW_W3 : W3/0 +* GPIOW_W4 : W4/0 +* GPIOW_W5 : W5/0 +* GPIOW_W6 : W10/0 +* GPIOW_W7 : W11/0 +* GPIOW_W8 : W12/0 +* GPIOW_W9 : W13/0 + +## JTAG + +JTAG + +* JTAG_TCK : E21/0 +* JTAG_TDI : E19/0 +* JTAG_TDO : E20/0 +* JTAG_TMS : E18/0 + +## MSPI0 + +SPI Master 1 (general) + +* MSPI0_CK : S28/1 +* MSPI0_MISO : S31/1 +* MSPI0_MOSI : S30/1 +* MSPI0_NSS : S29/1 + +## MTWI + +I2C Master 1 + +* MTWI_SCL : W31/1 +* MTWI_SDA : W30/1 + +## RG0 + +Gigabit Ethernet 0 + +* RG0_ECOL : N20/1 +* RG0_ECRS : N19/1 +* RG0_EMDC : N15/1 +* RG0_EMDIO : N16/1 +* RG0_ERXCK : N12/1 +* RG0_ERXD0 : N0/1 +* RG0_ERXD1 : N1/1 +* RG0_ERXD2 : N2/1 +* RG0_ERXD3 : N3/1 +* RG0_ERXDV : N14/1 +* RG0_ERXERR : N13/1 +* RG0_ETXCK : N18/1 +* RG0_ETXD0 : N8/1 +* RG0_ETXD1 : N9/1 +* RG0_ETXD2 : N10/1 +* RG0_ETXD3 : N11/1 +* RG0_ETXEN : N17/1 +* RG0_ETXERR : N21/1 + +## SDR + +SDRAM + +* SDR_AD0 : W13/1 +* SDR_AD1 : W12/1 +* SDR_AD10 : S0/1 +* SDR_AD11 : S1/1 +* SDR_AD12 : S2/1 +* SDR_AD2 : W11/1 +* SDR_AD3 : W10/1 +* SDR_AD4 : W5/1 +* SDR_AD5 : W4/1 +* SDR_AD6 : W3/1 +* SDR_AD7 : W2/1 +* SDR_AD8 : W1/1 +* SDR_AD9 : W0/1 +* SDR_BA0 : W15/1 +* SDR_BA1 : W14/1 +* SDR_CASn : S19/1 +* SDR_CKE : S17/1 +* SDR_CLK : S16/1 +* SDR_CSn0 : S21/1 +* SDR_D0 : W23/1 +* SDR_D1 : W22/1 +* SDR_D10 : S10/1 +* SDR_D11 : S11/1 +* SDR_D12 : S12/1 +* SDR_D13 : S13/1 +* SDR_D14 : S14/1 +* SDR_D15 : S15/1 +* SDR_D2 : W21/1 +* SDR_D3 : W20/1 +* SDR_D4 : W19/1 +* SDR_D5 : W18/1 +* SDR_D6 : W17/1 +* SDR_D7 : W16/1 +* SDR_D8 : S8/1 +* SDR_D9 : S9/1 +* SDR_DQM0 : W24/1 +* SDR_DQM1 : S3/1 +* SDR_RASn : S18/1 +* SDR_WEn : S20/1 + +## SYS + +System Control + +* SYS_PLLCLK : N28/0 +* SYS_PLLSELA0 : N29/0 +* SYS_PLLSELA1 : N30/0 +* SYS_PLLTESTOUT : N31/0 +* SYS_PLLVCOUT : E31/0 +* SYS_RST : N27/0 + +## UART0 + +UART (TX/RX) 1 + +* UART0_RX : S27/1 +* UART0_TX : S26/1 + +## VDD + +Power + +* VDDE_0 : W6/0 +* VDDE_1 : W28/0 +* VDDE_2 : S4/0 +* VDDE_3 : S25/0 +* VDDE_4 : E5/0 +* VDDE_5 : E25/0 +* VDDE_6 : N5/0 +* VDDE_7 : N26/0 +* VDDI_0 : W8/0 +* VDDI_1 : W26/0 +* VDDI_2 : S6/0 +* VDDI_3 : S23/0 +* VDDI_4 : E6/0 +* VDDI_5 : E23/0 +* VDDI_6 : N6/0 +* VDDI_7 : N24/0 + +## VSS + +GND + +* VSSE_0 : W7/0 +* VSSE_1 : W27/0 +* VSSE_2 : S5/0 +* VSSE_3 : S24/0 +* VSSE_4 : E4/0 +* VSSE_5 : E24/0 +* VSSE_6 : N4/0 +* VSSE_7 : N25/0 +* VSSI_0 : W9/0 +* VSSI_1 : W25/0 +* VSSI_2 : S7/0 +* VSSI_3 : S22/0 +* VSSI_4 : E7/0 +* VSSI_5 : E22/0 +* VSSI_6 : N7/0 +* VSSI_7 : N23/0 + +# Pinmap for Libre-SOC 2 (NGI Router) 180nm + +## UART0 + + + +* UART0_TX 90 S26/1 +* UART0_RX 91 S27/1 + +## JTAG + +* JTAG_TMS 50 E18/0 +* JTAG_TDI 51 E19/0 +* JTAG_TDO 52 E20/0 +* JTAG_TCK 53 E21/0 + +## PWM + + +## EINT + +* EINT_0 60 E28/2 +* EINT_1 61 E29/2 +* EINT_2 62 E30/2 + +## VDD + +* VDDE_6 5 N5/0 +* VDDI_6 6 N6/0 +* VDDI_7 24 N24/0 +* VDDE_7 26 N26/0 +* VDDE_4 37 E5/0 +* VDDI_4 38 E6/0 +* VDDI_5 55 E23/0 +* VDDE_5 57 E25/0 + +## VSS + +* VSSE_6 4 N4/0 +* VSSI_6 7 N7/0 +* VSSI_7 23 N23/0 +* VSSE_7 25 N25/0 +* VSSE_4 36 E4/0 +* VSSI_4 39 E7/0 +* VSSI_5 54 E22/0 +* VSSE_5 56 E24/0 + +## SYS + + + +* SYS_RST 27 N27/0 +* SYS_PLLCLK 28 N28/0 +* SYS_PLLSELA0 29 N29/0 +* SYS_PLLSELA1 30 N30/0 +* SYS_PLLTESTOUT 31 N31/0 +* SYS_PLLVCOUT 63 E31/0 + +## MTWI + +I2C. + + +* MTWI_SDA 126 W30/1 +* MTWI_SCL 127 W31/1 + +## MSPI0 + +* MSPI0_CK 92 S28/1 +* MSPI0_NSS 93 S29/1 +* MSPI0_MOSI 94 S30/1 +* MSPI0_MISO 95 S31/1 + +## RG0 + + + +* RG0_ERXD0 0 N0/1 +* RG0_ERXD1 1 N1/1 +* RG0_ERXD2 2 N2/1 +* RG0_ERXD3 3 N3/1 +* RG0_ETXD0 8 N8/1 +* RG0_ETXD1 9 N9/1 +* RG0_ETXD2 10 N10/1 +* RG0_ETXD3 11 N11/1 +* RG0_ERXCK 12 N12/1 +* RG0_ERXERR 13 N13/1 +* RG0_ERXDV 14 N14/1 +* RG0_EMDC 15 N15/1 +* RG0_EMDIO 16 N16/1 +* RG0_ETXEN 17 N17/1 +* RG0_ETXCK 18 N18/1 +* RG0_ECRS 19 N19/1 +* RG0_ECOL 20 N20/1 +* RG0_ETXERR 21 N21/1 + +## RG1 + + + +* RG1_ERXD0 32 E0/1 +* RG1_ERXD1 33 E1/1 +* RG1_ERXD2 34 E2/1 +* RG1_ERXD3 35 E3/1 +* RG1_ETXD0 40 E8/1 +* RG1_ETXD1 41 E9/1 +* RG1_ETXD2 42 E10/1 +* RG1_ETXD3 43 E11/1 +* RG1_ERXCK 44 E12/1 +* RG1_ERXERR 45 E13/1 +* RG1_ERXDV 46 E14/1 +* RG1_EMDC 47 E15/1 +* RG1_EMDIO 48 E16/1 +* RG1_ETXEN 49 E17/1 +* RG1_ETXCK 58 E26/1 +* RG1_ECRS 59 E27/1 + +## SDR + + + +* SDR_AD10 64 S0/1 +* SDR_AD11 65 S1/1 +* SDR_AD12 66 S2/1 +* SDR_DQM1 67 S3/1 +* SDR_D8 72 S8/1 +* SDR_D9 73 S9/1 +* SDR_D10 74 S10/1 +* SDR_D11 75 S11/1 +* SDR_D12 76 S12/1 +* SDR_D13 77 S13/1 +* SDR_D14 78 S14/1 +* SDR_D15 79 S15/1 +* SDR_CLK 80 S16/1 +* SDR_CKE 81 S17/1 +* SDR_RASn 82 S18/1 +* SDR_CASn 83 S19/1 +* SDR_WEn 84 S20/1 +* SDR_CSn0 85 S21/1 +* SDR_AD9 96 W0/1 +* SDR_AD8 97 W1/1 +* SDR_AD7 98 W2/1 +* SDR_AD6 99 W3/1 +* SDR_AD5 100 W4/1 +* SDR_AD4 101 W5/1 +* SDR_AD3 106 W10/1 +* SDR_AD2 107 W11/1 +* SDR_AD1 108 W12/1 +* SDR_AD0 109 W13/1 +* SDR_BA1 110 W14/1 +* SDR_BA0 111 W15/1 +* SDR_D7 112 W16/1 +* SDR_D6 113 W17/1 +* SDR_D5 114 W18/1 +* SDR_D4 115 W19/1 +* SDR_D3 116 W20/1 +* SDR_D2 117 W21/1 +* SDR_D1 118 W22/1 +* SDR_D0 119 W23/1 +* SDR_DQM0 120 W24/1 + +## Unused Pinouts (spare as GPIO) for 'Libre-SOC 2 (NGI Router) 180nm' + +| Pin | Mux0 | Mux1 | Mux2 | Mux3 | +| --- | ----------- | ----------- | ----------- | ----------- | +| 68 | S VDDE_2 | | | | +| 69 | S VSSE_2 | | | | +| 70 | S VDDI_2 | | | | +| 71 | S VSSI_2 | | | | +| 86 | S VSSI_3 | | | | +| 87 | S VDDI_3 | | | | +| 88 | S VSSE_3 | | | | +| 89 | S VDDE_3 | | | | +| 102 | W VDDE_0 | | | | +| 103 | W VSSE_0 | | | | +| 104 | W VDDI_0 | | | | +| 105 | W VSSI_0 | | | | +| 121 | W VSSI_1 | | | | +| 122 | W VDDI_1 | | | | +| 123 | W VSSE_1 | | | | +| 124 | W VDDE_1 | | | | +| 125 | W GPIOW_W21 | | | | + +# Reference Datasheets + +datasheets and pinout links +* +* +* + +* +* +* +* p8 +* +* +* +* ULPI OTG PHY, ST +* ULPI OTG PHY, TI TUSB1210 + +# Pin Bank starting points and lengths + +* E 32 32 4 +* N 0 32 4 +* S 64 32 4 +* W 96 32 4 -- 2.30.2