From 364ac771232bae22803595f02cca1bc062920a4a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 30 Jan 2022 21:11:09 +0000 Subject: [PATCH] tagset is a local Signal in ICache --- src/soc/experiment/icache.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index b98a9357..81e0d558 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -644,7 +644,7 @@ class ICache(FetchUnitInterface, Elaboratable): def icache_miss_clr_tag(self, m, r, replace_way, req_index, - tagset, cache_tags): + cache_tags): comb = m.d.comb sync = m.d.sync @@ -659,6 +659,7 @@ class ICache(FetchUnitInterface, Elaboratable): for i in range(NUM_WAYS): with m.If(i == replace_way): + tagset = Signal(TAG_RAM_WIDTH) comb += tagset.eq(cache_tags[r.store_index].tag) comb += write_tag(i, tagset, r.store_tag) sync += cache_tags[r.store_index].tag.eq(tagset) @@ -737,7 +738,6 @@ class ICache(FetchUnitInterface, Elaboratable): stall_in, flush_in = self.stall_in, self.flush_in inval_in = self.inval_in - tagset = Signal(TAG_RAM_WIDTH) stbs_done = Signal() comb += r.wb.sel.eq(-1) @@ -760,7 +760,7 @@ class ICache(FetchUnitInterface, Elaboratable): with m.Case(State.CLR_TAG, State.WAIT_ACK): with m.If(r.state == State.CLR_TAG): self.icache_miss_clr_tag(m, r, replace_way, - req_index, tagset, cache_tags) + req_index, cache_tags) self.icache_miss_wait_ack(m, r, replace_way, inval_in, cache_tags, stbs_done) -- 2.30.2