From 3b1a075e871d7c14ba9b2983183eb8a4a3916f5e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 6 Jul 2015 17:07:02 -0700 Subject: [PATCH] Coherence torture test for VM tests VM tests only support one core, so have the other cores hammer on the memory system to attempt to catch simple coherence regressions. --- env | 2 +- isa/Makefile | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/env b/env index 4f3e3a8..93cc8bf 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 4f3e3a8d62cc88040846436b9c505045f7303d88 +Subproject commit 93cc8bffa3244a8ab4b507594d453faeb344d3d9 diff --git a/isa/Makefile b/isa/Makefile index e4606d5..8f174d1 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -22,8 +22,9 @@ default: all RISCV_PREFIX=riscv64-unknown-elf- RISCV_GCC = $(RISCV_PREFIX)gcc -RISCV_GCC_OPTS = -static -fpic -fvisibility=hidden -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha -RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data +ENTROPY = -DENTROPY=$(shell echo $$$$) +RISCV_GCC_OPTS = $(ENTROPY) -static -fpic -fvisibility=hidden -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha +RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data RISCV_SIM = spike --extension=hwacha vpath %.S $(isa_src_dir) -- 2.30.2