From 3da639e6391b6242b9f04844cef0978947b59187 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Jun 2018 10:53:16 +0100
Subject: [PATCH] clarify

---
 simple_v_extension/simple_v_chennai_2018.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 7017060fd..5a9beecc9 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -445,7 +445,7 @@ def get\_pred\_val(bool is\_fp\_op, int reg):
   \end{itemize}
   Notes:\vspace{10pt}
    \begin{itemize}
-   \item Same notes apply (previous slide) as for predication CSR table
+   \item References different (internal) mapping table for INT or FP
    \item Level of indirection has implications for pipeline latency
   \end{itemize}
 }
-- 
2.30.2